Intel Corporation

Brent S Stone

Kaladhar Radhakrishnan

Hong Xie

Dustin P Wood

Raj Nair

Tim Gates

Robert L Sankman

Debendra Mallik

Sanjay Dabral

Ram S Viswanath

Joshua Heppner

Rajasekaran Swaminathan

Donald Tiendung Tran

Gregorio R Murtagian

Michael Walk

Kris Frutschy

Joel A Auernheimer

Glenn E Stewart

Lesley A Polka

Radha R Kanaparthy

Embodiments of the present disclosure are directed towards an inductor structure having one or more strips of conductive material disposed around a core. The strips may have contacts at a first end and a second end of the strips, and may be disposed around the core with a gap between the contacts. The inductor structure may be mounted on a surface of a substrate, and one or more traces may be formed in the surface of the substrate to electrically couple two or more of the strips of conductive material to one another to form inductive coils. Other embodiments may be described and/or claimed.

Surface-mount inductor structures for forming one or more inductors with substrate traces

This disclosure relates generally to a chip package assembly arranged to be electrically coupled to a circuit board including a plurality of circuit board contacts. The chip package assembly may include a chip package including a first side and a second side, the second side including a first plurality of contacts arranged to be electrically coupled to the plurality of circuit board contacts and a second plurality of contacts arranged to be electrically coupled to a remote device via a connector assembly.

Chip package connector assembly

An LGA socket for receiving substrate packages of various sizes and a method of fabricating the socket. In an embodiment, the socket has a planar surface for seating a substrate package. Socket contacts are disposed on the planar surface in a layout common to the layout of interconnects formed on the bottom of substrate packages the socket is designed to receive. A plurality of socket locating features is formed on the socket body to prevent lateral displacement of a reference substrate package. A corresponding number of package locating features are formed on the substrate body of packages larger than the reference substrate package. Each of the socket locating features meshes with the corresponding package locating feature of the larger package.

Land grid array (LGA) socket for various package sizes

An integrated circuit package includes a first capacitor supported by a surface of a substrate, and a second capacitor supported by the surface of the substrate. The first capacitor is within a die shadow region, and the second capacitor lies outside of the die shadow region.

Integrated circuit packages, systems, and methods

A hybrid electronic circuit package (FIG.) includes non-insertable conductive features () and insertable conductive features () at a surface of the package. A hybrid receptacle (), such as a socket, for example, includes non-insertable contacts () and insertable contacts (), which are positioned in a complementary manner with the non-insertable and insertable features of the package. A vertical securement device () applies a vertical compressive force to the package () to compress the non-insertable features () against the non-insertable contacts (). Further, a normal force securement device can be used to provide a sustained normal force to compress the insertable features and contacts together. In one embodiment, the non-insertable features are land grid array lands and the insertable features are low insertion force features.

Hybrid package with non-insertable and insertable conductive features, complementary receptacle, and methods of fabrication therefor

A electrical interface for an electronic package, using lands on the package which are non-planar with metal layers within the package. This non-planar or tilted land grid array (TLGA) package is assembled with a complementary TLGA socket to make electronic connection to the package.

Tilted land grid array package and socket, systems, and methods

A socket and package apparatus are disclosed for increasing the amount of power that can be delivered from an IC board to an IC where the IC package is mounted in a socket connected to the IC board. In one embodiment, the IC package includes a first power plane along with a power carrier and one or more pin receptacles. The power bar carrier includes a first conducting panel that is electrically coupled to the first power plane along a first adjacent edge. The first conducting panel is also electrically coupled to a first plurality of conducting pads.

System and apparatus for socket and package power/ground bar to increase current carrying capacity for higher IC power delivery

A grounded conductive plate in a land grid array package assembly includes a plurality of openings. The openings allow contacts from the socket to pass through to contact a package. The diameter of each opening is customizable to produce desired impedance between the contacts and the conductive plate. Impedance discontinuity seen by signals passing through the socket may be reduced.

Land grid array with socket plate

A hybrid electronic circuit package (, FIG.) includes non-insertable conductive features () and insertable conductive features () at a surface of the package. A hybrid receptacle (), such as a socket, for example, includes non-insertable contacts () and insertable contacts (), which are positioned in a complementary manner with the non-insertable and insertable features of the package. A vertical securement device () applies a vertical compressive force to the package () to compress the non-insertable features () against the non-insertable contacts (). Further, a normal force securement device can be used to provide a sustained normal force to compress the insertable features and contacts together. In one embodiment, the non-insertable features are land grid array lands and the insertable features are low insertion force features.

Hybrid package with non-insertable and insertable conductive features, complementary receptacle, and methods of fabrication, assembly, and operation therefor

A fabrication method and semiconductor package provide enhanced performance. The semiconductor package includes a semiconductor die having an integrated circuit (IC), and a substrate having a die side coupled to the IC. A plurality of multi-signal bus bars is coupled to a socket side of the substrate such that the bus bars enable I/O signals to be transported between the substrate and a socket.

Semiconductor package having multi-signal bus bars

A socket cover with a recessed center, method for using such a socket cover and system using such a socket cover are described herein.

Socket cover with recessed center and method

A socket and package apparatus are disclosed for increasing the amount of power that can be delivered from an IC board to an IC where the IC package is mounted in a socket connected to the IC board. The apparatus has two separable and distinct parts designed to electrically engage. The package is designed with a power bar where the panels of the power bar are permanently and electrically connected to various power planes of the IC package along its entire adjacent wall. The socket is designed with a power bar carrier designed to maximize the current flow from the IC board to the power bar. The package is then engaged into the socket.

Socket and package power/ground bar apparatus that increases current carrying capacity resulting in higher IC power delivery

A system may include an integrated circuit package having a package power contact and a package ground contact, and an interposer to physically receive a portion of the package and including a lip. A system may also include a first card having a card power contact to interface with the package power contact and a card ground contact to interface with the package ground contact, where the first card defines an opening to receive a portion of the interposer, and the lip is to support a portion of the first card.

Integrated circuit packaging architecture

The present invention relates to apparatus and methods for providing a low resistance power supply to a microelectronic package through the use of dual conductive paths. A first conductive path contained within the substrate and supplies current, primarily in responding to transient current demands to the microelectronic package. A lower resistance second conductive path supplies primarily steady state current to the microelectronic package through an electrical connection to an edge of the microelectronic package. Resistance in the second conductive path is reduced by using a power clamp to connect the second power supply to the microelectronic package.

Growing community of inventors

Chandler, AZ, United States of America

Brent S Stone