Cypress Semiconductor Corporation

Maxim Integrated Products, Inc.

Quantance, Inc.

Voxtel, Inc.

Brent R Jensen

Mark R Gehring

Serge Francois Drogi

George M Williams

Nathan Y Moyal

Martin Tomasz

Adam Lee

Benjamin J McCarroll

David W Entrikin

Russell R Moen

James W Marsh

Joseph D Stenger

Jehyuk Rhee

An imaging device is disclosed, the device comprising a pixelated array of semiconductor elements, in which each detecting element is electrically connected to an integrated circuit, the integrated circuit comprising a passive signal path and an active signal path. The passive path provides consecutive frame imaging and the active path detects the location of transient events. The device further comprising a readout decoder block, the readout decoder block controlling operation of the passive paths. Additionally, the device comprises of an address arbitration control block, the address arbitration control block controlling operation of the active paths, wherein the address arbitration control block readout of the active paths are independent of readout of the integrated signal readout from the passive paths.

Asynchronous readout array

A power supply system uses improved Class G amplifier architecture for high bandwidth operation with low distortion. The power supply system switches between multiple power supply rails, depending on the signal level handled by the power supply system. The lowest usable supply rail voltage is chosen to minimize power dissipation in the output driver, thus optimizing efficiency. Each supply rail has an associated driver capable of sourcing current to the amplifier output. When a supply rail is selected, its associated driver is enabled and other driver(s) not associated with the selected supply rail are disabled via separate disable control signals. The disabling of the deselected driver may be delayed until current above a predetermined threshold is sensed at the output of the enabled driver. In addition, the frequency of switching between the power rails may be limited via various means designed to limit distortion in the power supply system.

High bandwidth power supply system with high efficiency and low distortion

A circuit including a subcircuit having differential signals, and a feedback circuit coupled to the subcircuit. The feedback circuit is configured to measure an offset between the differential signals, to generate a calibration signal in response to the measurement, and to reduce the offset in response to the calibration signal.

Apparatus and method for calibrating mixer offset

A transmitter digital signal processor (DSP) circuit has a transmit frequency represented by n-bit data output from a look up table (LUT). The n-bit data is outputted to an n-bit accumulator structured to overflow at a rate based on the output n-bit data to output a phase. The circuit further has device structured to add an n-bit signed constant to the accumulator to offset the frequency represented by the n-bit data output from the LUT. A transceiver on a semiconductor chip may include as part of a transmitter circuit, a transmit DSP circuit that has the LUT, accumulator and device providing an n-bit signed constant to the accumulator to offset a transmit frequency in order to allow a receiver circuit on the transceiver to communicate directly with the transmitter circuit, and thus allowing testing of the transceiver.

Frequency offset and method of offsetting

A method and apparatus to synchronize a boost signal. The apparatus includes a boost circuit and a synchronization circuit. The synchronization circuit is coupled to the boost circuit. The boost circuit generates an unsynchronized boost signal to boost a voltage signal from a first voltage to a second voltage. The synchronization circuit synchronizes the unsynchronized boost signal with a reference signal to generate a synchronized boost signal.

Synchronized boost signal apparatus and method

A system and method of testing switch functionality of a tunable capacitor array is disclosed. A built in test (BIT) circuit provides digital device for testing the functionality of a programmable switch capacitor array circuit. The method and system provides for switching a capacitor switch of a switch capacitor array between on and off, switching a test enable switch of a BIT circuit between on and off, pulling an internal node of the BIT circuit either high or low using a current source, and determining whether the internal node has been pulled either high or low. In addition, the method and system provides for making a pass or fail determination based on a determined state of the internal node.

Method and system for built in testing of switch functionality of tunable capacitor arrays

A method and system for calibrating a time constant within an integrated circuit. A voltage storage element is charged, and the time required to achieve a reference voltage on the storage element is measured. The measured time is compared to a desired time. It necessary, an adjustable impedance is modified to change the charging time, and the cycle may be repeated until the charging time matches the desired time. In this novel manner, an actual RC time constant, as rendered in a particular integrated circuit, is measured and potentially adjusted to match a desired time constant. Advantageously, configuration information of the adjustable impedance may be communicated to other circuitry within the integrated circuit to enable such circuitry to implement the same RC time constant in analog signal processing. Consequently, embodiments of the present invention overcome incidences of wide tolerance in passive components implemented in integrated circuits. Beneficially, no external test equipment is required.

Calibration of integrated circuit time constants

A method and an apparatus are described for providing biasing for an amplifier. In an embodiment invention, a bias network comprises an integration circuit to sense a voltage change for an amplifier. The bias network adjusts a bias voltage for the amplifier in response to the voltage change.

Amplifier biasing

A method for obtaining a rectified signal from a first alternating current signal. The method includes the step of inputting the first alternating current signal into a variable gain amplifier to obtain a second alternating current signal. The second alternating current signal has a substantially constant peak-to-peak voltage irrespective of a power level of the first alternating current signal. The method further includes the step of rectifying the second alternating current signal, using a power detector circuit, to obtain the rectified signal, whereby a direct current level of the rectified signal is substantially proportional to the power level of the first alternating current irrespective of the power level of the first alternating current. The rectified signal may then be employed in, for example, a feedback control circuit to control the amount of power output by an RF signal source.

Methods and apparatus for signal amplitude control systems

A temperature compensated logarithmic detector biased with a proportional to absolute temperature (PTAT) voltage produced in accordance with an area ratio of biasing transistors is disclosed. According to one implementation of the invention, the temperature compensated logarithmic detector includes biasing circuitry and a logarithmic detector cell. The biasing circuitry receives an input signal and produces a PTAT bias voltage from the input signal. The PTAT characteristic of the PTAT bias voltage is produced by an area ratio. The logarithmic detector cell converts the input signal to a logarithmic output signal in accordance with a logarithmic transfer function over a narrow range.

Temperature compensated logarithmic detector

A current source includes a control stage responsive to a stable, d.c. input voltage that is operative to produce a control voltage proportional to absolute temperature (PTAT), and an output stage responsive to the PTAT control voltage that is operative to produce an output current that is an essentially constant fraction of an output constant current source. The control stage includes a temperature-dependent control resistor of a given resistor type, and at least one control constant current source providing the control resistor with a temperature dependent control current. The temperature dependent current source includes a temperature dependent current source resistor based on the given resistor type such that the temperature dependencies of the control current and the control resistor tend to cancel in such a manner that a true PTAT control voltage is developed. The output stage includes an output transistor coupled to an output constant current source such that an output current of the output stage has no current contribution other than from the output current source. A method for providing a current that is a constant fraction of an output constant current source includes the steps of: (a) developing a control current that is based on the same resistor type as a control resistor; (b) applying the control current to the control resistor to develop a control voltage that is proportional to absolute temperature; and (c) applying the control voltage to a current divider coupled to an output constant source to provide an output current.

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Portland, OR, United States of America

Brent R Jensen