Intel Corporation

Other

Brent R Carlton

Stefano Pellerano

Somnath Kundu

Stewart S Taylor

Mustafijur Rahman

Amy Whitcombe

Christopher Hull

Hao Luo

Abhishek Agrawal

Renzhi Liu

Asma Beevi Kuriparambil Thekkumpate

Ritesh Bhat

Xu Zhang

Jing Zhu

Nageen Himayat

Shilpa Talwar

Hosein Nikopour

Ofir Degani

Nasser A Kurd

Ehud Reshef

Jing-Hong Conan Zhan

Tarek A Ibrahim

Oner Orhan

Mohamed A Abdelmoneum

Rinkle Jain

Ehsan Aryafar

Whitney Michael Bryks

Jason A Mix

Ronen Kronfeld

Eduardo Alban

Sarit Zur

Srinivas Venkata Ramanuja Pietambaram

Peter Sagazio

Navid Naderializadeh

Xuebin Yang

Ofer Benjamin

Woorim Shin

Steven Callender

Jingyi Ma

Donald T Comer

Eli Borokhovich

Sarah Shahraini

An electronic device and associated methods are disclosed. In one example, the electronic device includes a MEMS die located within a substrate, and below a processor die. In selected examples, the MEMS die includes a resonator. Example methods of forming MEMS resonator devices are also shown.

Integrated MEMS resonator and method

A transceiver may include a transmit path and a receive path that are each coupled to a radio frequency (RF) interface, and a self-interference canceller (SIC). The SIC is coupled between the transmit and the receive paths. The SIC is configured to cancel a self-interference signal from a received signal on the receive path based on a transmit signal on the transmit path.

Self-interference canceller

An apparatus can include a digital-to-analog converter (DAC) and calibration circuitry including an oscillator. The calibration circuitry can be coupled to an output of the DAC, the calibration circuitry to sample and count DAC output pulses for at least two consecutive pulses using at least two separate counter circuits. The calibration circuitry can determine error between at least two consecutive pulses and provide a correction value based on the error. The apparatus can further include correction circuitry to provide a calibration signal to the DAC based on the correction value.

High-speed digital-to-analog converter calibration

A differential voltage-to-time converter (VTC) architecture and method of providing VTC signals are disclosed. The VTC includes a ramp generator that generates a ramp voltage, capacitors having a bottom plate coupled with the ramp generator to receive the ramp voltage, and inverters having inputs coupled to top plates of the capacitors to provide signals based on a sampled signal. A threshold voltage or supply voltage of the inverters tracks a minimum input signal voltage.

Low noise inverter-based voltage-to-time converter with common mode input tracking

A digital-to-time converter (DTC)-based open loop frequency synthesis and calibration circuit may be used to provide a precise clock signal. The DTC calibration circuit may include a DTC to generate a DTC clock signal based on a received input clock frequency and a received initial digital input code, a phase-lock loop (PLL) to generate a PLL clock signal based on a received PLL input, a binary phase-detector (PD) to generate a PD output based on a comparison between the DTC clock signal and the PLL clock signal, a plurality of calibration bins to generate a signed accumulated PD portion based on the PD output, and an adder to generate a calibrated DTC input code based on a combination of the signed accumulated PD portion and a subsequent digital input code, where the DTC generates a calibrated clock signal based on the calibrated DTC input code.

Calibration for DTC fractional frequency synthesis

An apparatus and method are provided to re-configure an existing low-jitter phase locked loop (PLL) circuit for fast start-up during system wake-up. During system start-up, a feed-back path of the PLL is disconnected to independently control the VCO frequency. This independently controlled VCO then injects energy into a resonator (e.g., a crustal oscillator) for its fast start-up. Once a resonance frequency of the resonator is detected and an oscillation builds up in the resonator, a VCO control voltage is stored. The PLL feedback is then restored and the stored VCO control voltage is applied to perform phase-locking operation. Since the PLL control voltage is already set to the desired operating point, the PLL lock time is very small.

Phase locked loop assisted fast start-up apparatus and method

Various aspects provide a transceiver and a communication device including the transceiver. In an example, the transceiver includes an amplifier circuit including an amplifier stage with an adjustable degeneration component, the amplifier stage configured to amplify a received input signal with an adjustable gain, an adjustable feedback component coupled to the amplifier stage; and a controller coupled to the amplifier stage and to the adjustable feedback component and configured to adjust the adjustable feedback component based on an adjustment of the adjustable degeneration component.

Communication device

A time-to-digital converter (TDC) that combines the energy efficiency of a successive approximation (SAR) design with the high speed of pipelined converters by leveraging the inherently pipelined nature of time-domain signaling. The TDC achieves high speed by removing a comparator decision from a signal path, instead using AND/OR gates to separate early and late edges. The TDC uses a pipelined SAR architecture to digitize a differential delay between two incoming clock edges with high speed and low power consumption. Described is a modular digital reference voltage generator that can be used for a capacitive digital-to-analog converter (DAC). The generator comprises a decoupling capacitor, one or more clocked comparators, and power transistor(s). A simplified digital low dropout (LDO) circuitry is used to provide fast reference voltage generation with minimal overhead. The LDO circuitry is arrayed using time-interleaved synchronous clocks or staggered asynchronous clocks to provide finer timing resolution.

Time-to-digital converter and comparator-based reference voltage generator

A transceiver may include a transmitter device, a receiver device, a secondary receiver device, and switching elements. The transmitter device may provide a transmit control signal on first and second channels. The receiver device may receive a receive control signal on the first and second channels. The secondary receiver device may monitor occupation of the first and second channels without decoding at least a portion of control signals concurrent with the receiver device receiving the receive control signal. The switching elements may control when the transmitter device provides the transmit control signal to one of and is electrically isolated from first and second antennas, the receiver device receives the receive control signal from one of and is electrically isolated from the first and second antennas, and the secondary receiver device monitors occupation of one of the first and second channels and is electrically isolated from the first and second antennas.

Wireless communication within a control plane and a data plane

Methods, apparatus, and computer-readable media are described to use multi-finger beamforming for multimeter wave communications. A base station associates with first and second user equipment. Weight sum rates are determined for the user equipment. Transmissions are scheduled to the user equipment based on the weight sum rates. Data is encoded for the first user equipment and transmitted based on the schedule. Data is encoded for the second user equipment and transmitted based on the schedule. The transmissions are multiplexed in the power domain.

Non-orthogonal multiple-access and multi-finger beamforming

A reference sampling Type-I fractional-N PLL directly samples the reference clock and therefore does not use a reference buffer. Here, a phase-detector is a passive sampling switch which neither consumes any power nor generates any noise. Therefore, all the major contributors of in-band phase-noise are eliminated by the reference sampling Type-I fractional-N divider. A double sampling phase-detector with a switched-capacitor passive voltage interpolator circuit is used to achieve fractional-N output. To achieve a high resolution of the voltage interpolator or the switched capacitor, a sigma-delta modulator is used.

Reference sampling Type-I fractional-N phase locked loop

An apparatus injects a start clock to a crystal at the beginning to increase an overall start up speed of the crystal. The apparatus relies on an impedance change inside the crystal itself instead of searching for a synchronization on the yet small crystal oscillation. The apparatus includes an oscillator (separate from the crystal) to search for the crystal's resonance frequency by detecting the crystal's impedance change. Once the frequency of the oscillator matches the crystal's resonance, there is significant change in the crystal's impedance. Using that information, the apparatus can lock the oscillator frequency at the crystal resonance frequency and inject the clock with high efficiency.

Fast start-up crystal oscillator

A communication device can include a receiver frontend and a wake-up receiver (WUR) frontend. The receiver frontend can have a radio frequency (RF) interface configured to couple to an antenna and a baseband interface configured to couple to a baseband component. The WUR frontend can be selectively coupled to the receiver frontend (e.g. between the RF interface and the baseband interface). The WUR frontend may monitor a communication channel and control the receiver frontend to adjust its operating mode (e.g. waking the receiver frontend from a sleep mode) based on the monitoring. The WUR frontend may have a lower power consumption than the receiver frontend. The WUR frontend and the receiver frontend may share the same impedance matching network and/or the RF interface.

Communication system including a wake-up radio

Systems, methods, and circuitries are disclosed for performing self-interference cancellation in a transceiver. In one example, a self-interference cancellation system includes a cancellation signal circuitry, cancellation circuitry, down-conversion circuitry, and an LO derivation circuitry. The cancellation signal circuitry is configured to use a cancellation transmit (TX) local oscillator (LO) signal to up-convert a baseband transmit leakage replica signal to generate a cancellation signal. The cancellation circuitry is configured to combine the cancellation signal with a received signal to generate a corrected received signal. The down-conversion circuitry is configured to use a receive (RX) LO signal to down-convert the corrected received signal to generate a baseband received signal. The LO derivation circuitry is configured to derive the cancellation TX LO signal and the RX LO signal from a common LO signal.

Self-interference cancellation system and method

Embodiments of apparatuses, articles, methods, and systems for calibrating receive chain to reduce second order intermodulation distortion are disclosed herein. In some embodiments, a reference sensing chain is used to generate reference second-order intermodulation distortion signals that may be used to adjust a calibration code. In some embodiments, a calibration code may be adjusted using one or more feedback loops of a baseband amplifier. The embodiments may be employed, e.g., to manage power in wireless networks. Other embodiments and usages may be described and claimed.

Growing community of inventors

Hillsboro, OR, United States of America

Brent R Carlton