Synopsys, Inc.

Brent L Gregory

Russell B Segal

William Clark Naylor, Jr

Bogdan Craciun

Jing Chyuarn Lin

Paul Il Estrada

Emil F Girczyc

Andrew Seawright

Srinivas Raghvendra

Trinanjan Chatterjee

Jagat B Patel

Jaime Wong

Systems and techniques for optimizing an integrated circuit (IC) design are described. Some embodiments can transform a circuit design into a logically-equivalent circuit design by: (1) creating a Wire-Length-Area Model (WLAM) for a portion of a first circuit design, (2) creating a second circuit design by replacing the portion of the first circuit design by the WLAM, (3) placing and routing the second circuit design to obtain a placed-and-routed second circuit design, and (4) creating a third circuit design that is logically-equivalent to the first circuit design based on the placed-and-routed second circuit design.

Placement-based congestion-aware logic restructuring

A method of optimizing a netlist for a circuit comprising identifying a logic tree with a single output and a plurality of interchangeable inputs, and calculate the optimal permutation of the plurality of inputs. The method further comprising modify the netlist based on the optimal permutation, and optimizing the modified netlist.

Optimizing the ordering of the inputs to large commutative-associative trees of logic gates

An automated design process using a computer system includes identifying a set of timing endpoints in a circuit defined by a machine-readable file. Values of slack in the estimated arrival times for the timing endpoints are assigned. Probability distribution functions, such as Gaussian distributions, are assigned for the respective values of slack, and are combined. The combination of probability distribution functions represents a measure of circuit performance. The measure is computed for alternative implementations of the circuit, and used to identify an alternative more likely to meet timing constraints.

Automation method and system for assessing timing based on gaussian slack

Automation method and system for assessing timing based on Gaussian slack

This invention provides a method for displaying circuit analysis results corresponding to parts of the circuit near the portion of the hardware description language (HDL) specification that generated that part of the circuit. The invention also includes a method for using probe statements in the HDL specification to mark additional points in the initial circuit that should not be eliminated during optimization. This improves the ability to display circuit analysis results near the appropriate part of the HDL specification.

Architecture and methods for a hardware description language source

A method and system are provided for generating a logic network using a hardware independent description means. A logic circuit synthesizer, in response to a user description specifying only signals and the circumstances under which the signals are produced, generates a logic network that generates the signals specified in the user description, e.g., a net list of logic elements, such as logic gates, high impedance drivers, level sensitive latches and edge sensitive flip-flops along with the interconnections of the logic elements. In one embodiment, the logic circuit synthesizer includes a preprocessor means and a logic circuit generator means. The preprocessor means, in response to the user description, converts signals and conditions in the user description into a structure having nodes interconnected by edges. The edges include an edge condition under which the edge is traversed. The logic circuit generator, using the structure and the edge conditions, creates a logic network that generates the signals specified in the user description.

Method for processing a hardware independent user description to

A digital circuit is synthesized from a text description of a digital system. During synthesis, a parse tree with parse nodes is constructed and retained. The relationship between the parse nodes and the circuit elements synthesized from those parse nodes is retained. Using that relationship, analysis results associated with circuit elements can be related to the text that generated those circuit elements. In particular, the analysis results can be used to set the display characteristics, such as font or size, of the text associated with those results.

A method and apparatus for displaying text which efficiently couples information derived from the parse tree for the text with the display of the text. Use of parse tree information allows the system to display different parts of the text in a context-sensitive manner. The method involves creating a parse array from a parse tree for the text. The parse array contains a compressed representation of the nodes of the parse tree. This parse array is used to find the parse node which corresponds to a particular location in the text. The parse array can be traversed to a chosen character using a stack. In one embodiment the stack can be saved periodically to improve performance so that the parse node corresponding to a character can be more quickly determined. The parse array is also used to find the entire portion of the text which corresponds to the parse node. The text corresponding to a particular parse node is displayed with a display characteristic which differentiates this portion of the text from the remainder of the text. Thus, a user of this display can view the text in a context-sensitive fashion.

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Sunnyvale, CA, United States of America

Brent L Gregory