Micron Technology Incorporated

Round Rock Research, LLC

Other

Micron Semiconductor, Inc.

Advanced Memory International, Inc.

Mircon Technology, Inc.

Mycron Technology, Inc.

Brent Keeth

Troy A Manning

Brian L Johnson

Chris G Martin

Layne G Bunker

James Brian Johnson

Feng Lin

Kevin J Ryan

Joe M Jeddeloh

Charles H Dennison

Scott James Derner

Pierre C Fazan

Terry R Lee

Frank F Ross

Jeffery W Janzen

Brian M Shirley

Raymond J Beffa

Roy Edgar Greeff

Paul S Zagar

Ronnie M Harrison

Joo S Choi

Naveh Malihi

Gurtej S Sandhu

Salman Akram

Durai Vishak Nirmal Ramaswamy

David J Corisis

Scott E Sills

Richard Cameron Murphy

Stephen L Casper

John Frederic Schreck

Seong-Hoon Lee

Adam D Johnson

Alessandro Calderoni

Russel J Baker

Mark E Tuttle

Larry Duane Kinsman

Timothy B Cowles

Jeffrey P Wright

Adrian E Ong

Paul A LaBerge

Owen R Fay

Jaspreet Singh Gandhi

Chan H Yoo

Jian Li

Xiao Li

David L Pinney

Luke G England

Shijian Luo

Paul A Silvestri

Steven K Groothuis

Matthew B Leslie

Elliott Clifford Cooper-Balis

Mark Hiatt

James S Cullum

Walter L Moden

John K Zahurak

Eugene H Cloud

Matthew Alan Prather

William K Waller

Lei Bi

James M Shaffer

Jeffrey W Janzen

Leonard Forbes

Tony M Brewer

Timothy Mowry Hollis

Todd A Merritt

Peter B Gillingham

Fatma Arzum Simsek-Ege

Shubneesh Batra

David K Ovard

David V James

George Edward Pax

Michael Amiel Shore

Joseph C Sher

Christopher K Morzano

Cormac Michael O'Connell

Suraj J Mathew

Randall J Rooney

Bruce Millar

Eiichi Nakano

Fuad Badrieh

Michael D Chaine

Robert B Kerr

Dragos Dimitriu

Ebrahim H Hargan

Vinay Nair

Adam Saleh El-Mansouri

Diem Thy N Tran

Jacob D Baker

Greg King

Jasper S Gibbons

Kunal R Parekh

Sujeet V Ayyapureddi

Thomas W Voshell

Yoshikazu Morooka

Wallace E Fister

Kim M Pierce

Henry Stracovsky

Desi Rhoden

Donald N North

Apparatuses and methods related to managing regions of memory are described. Managing regions can include verifying whether an access command is authorized to access a particular region of a memory array, which may have some regions that have rules or restrictions governing access (e.g., so-called 'protected regions'). The authorization can be verified utilizing a key and a memory address corresponding to the access command. If an access command is authorized to access a region, then a row of the memory array corresponding to the access command can be activated. If an access command is not authorized to access the region, then a row of the memory array corresponding to the access command may not be activated.

Protected regions management of memory

The present disclosure provides techniques for using a multiple-port buffer to improve a transaction rate of a memory module. In an example, a memory module can include a circuit board having an external interface, first memory devices mounted to the circuit board, and a first multiple-port buffer circuit mounted to the circuit board. The first multiple-port buffer circuit can include a first port coupled to data lines of the external interface, the first port configured to operate at a first transaction rate, a second port coupled to data lines of a first plurality of the first memory devices, and a third port coupled to data lines of a second plurality of the first memory devices. The second and third ports can be configured to operate at a second transaction rate, wherein the second transaction rate is slower than the first transaction rate.

Memory module multiple port buffer techniques

Apparatus and methods are disclosed, including memory devices and systems. Example memory devices, systems and methods include a buffer interface to translate high speed data interactions on a host interface side into slower, wider data interactions on a DRAM interface side. The slower, and wider DRAM interface may be configured to substantially match the capacity of the narrower, higher speed host interface. In some examples, the buffer interface may be configured to provide multiple sub-channel interfaces each coupled to one or more regions within the memory structure and configured to facilitate data recovery in the event of a failure of some portion of the memory structure. Selected example memory devices, systems and methods include an individual DRAM die, or one or more stacks of DRAM dies coupled to a buffer die.

Memory device interface and method

Apparatus and methods are described, including memory devices and systems. Memory devices, systems and methods may include a buffer interface to translate high speed data interactions on a host interface side into slower, wider data interactions on a DRAM interface side. The slower, and wider DRAM interface may be configured to substantially match the capacity of the narrower, higher speed host interface. In some cases, the buffer interface may be configured to provide multiple sub-channel interfaces each coupled to one or more regions within the memory structure and configured to facilitate data recovery in the event of a failure of some portion of the memory structure. Selected memory devices, systems and methods may include an individual DRAM die, or one or more stacks of DRAM dies coupled to a buffer die.

Methods, systems, and devices for memory with parallel main and test interfaces are described. A memory die may be configured with parallel interfaces that may individually (e.g., separately) support evaluation operations (e.g., before or as part of assembly in a multiple-die stack) or access operations (e.g., after assembly in a multiple die stack). For example, a memory die may include a first set of one or more contacts that support communicating signaling with or via another memory die in a multiple-die stack. The memory die may also include a second set of one or more contacts that support probing for pre-assembly evaluations, which may be electrically isolated from the first set of contacts. By implementing such parallel interfaces, evaluation operations may be performed using the second set of contacts without damaging the first set of contacts, which may improve capabilities for supporting a multiple-die stack in a memory device.

Memory with parallel main and test interfaces

Methods, systems, and devices for buffer configurations for communications between memory dies and a host device are described. A memory device may include a buffer having a first interface coupled with a host device and a second interface coupled with a memory die of the memory device. The first interface may communicate information with the host device at a first frequency and according to a first signaling scheme, and the second interface may communicate information with the memory die at a second frequency and according to a second signaling scheme. The first frequency may be higher than the second frequency, and the second signaling scheme may include a greater quantity of voltage levels than the first signaling scheme.

Buffer configurations for communications between memory dies and a host device

Apparatus and methods are disclosed, including memory devices and systems. In an example, a memory module can include a first stack of at least eight memory die including four pairs of memory die, each pair of the four pairs of memory die associated with an individual memory rank of four memory ranks of the memory module, a memory controller configured to receive memory access commands and to access memory locations of the first stack, and a substrate configured to route connections between external terminations of the memory module and the memory controller.

Apparatus and methods are disclosed, including memory devices and systems. Example memory devices, systems and methods include a stack of memory dies, a controller die, and a buffer. Example memory devices, systems and methods include one or more neuromorphic layers logically coupled between one or more dies in the stack of memory dies and a host interface of the controller die.

Neuromorphic memory device and method

The present disclosure includes apparatuses and methods related to a memory expansion card suitable for, relative to other memory solutions, a high-speed interface and low power consumption. The memory expansion card can have on-die error correction code (ECC) circuitry and, in some examples, additional on-board circuitry, components, or capability to manage, relative to other memory solutions, a large number of volatile or non-volatile memory devices. A memory expansion card may have a controller with a host interface capable of using or defined according to a quantity of bits (i.e., a bit width), which may be eight bits. The controller may coupled to memory devices via several channels, and each channel may have the bit width of the interface.

Memory expansion card

Systems, apparatuses, and methods related to memory device protection are described. A quantity of errors within a memory device can be determined and the determined quantity can be used to further determine whether to utilize single or multiple memory devices for an error correction and/or detection operation. Multiple memory devices need not be utilized for the error correction and/or detection operation unless a quantity of errors within the memory device exceeds a threshold quantity.

Memory device protection

Methods, systems, and devices for multi-purpose signaling for a memory system are described. One or more signal paths of between a host device and a memory device may be configured to support shared pathways between multiple channels and to support multiple functions. For example, a signal path may be configured to communicate a state signal for an initialization sequence of the memory device, an error signal for the memory device to indicate that errors have occurred, or a low-power signal for the host device to request that the memory device enter a low-power mode, or a combination thereof. The signal path may be shared between two or more channels of the memory device.

Multi-purpose signaling for a memory system

Some embodiments include apparatus, systems, and methods having a base, a first die, a second arranged in a stacked with the first die and the base, and a structure located in the stack and outside at least one of the first and second dice and configured to transfer signals between the base and at least one of the first and second dice.

Signal delivery in stacked device

Memory devices, systems and methods include a buffer interface to translate high speed data interactions on a host interface side into slower, wider data interactions on a DRAM interface side. The slower, and wider DRAM interface may be configured to substantially match the capacity of the narrower, higher speed host interface. In some configurations, the buffer interface may be configured to provide multiple sub-channel interfaces each coupled to one or more regions within the memory structure and configured to facilitate data recovery in the event of a failure of some portion of the memory structure. Selected memory devices, systems and methods include an individual DRAM die, or one or more stacks of DRAM dies coupled to a buffer die.

Methods, systems, and devices for memory with fine grain architectures are described. An apparatus may include a memory device, a first organic substrate, and a second organic substrate. The first organic substrate may include a plurality of first conductive lines arranged with a first pitch that may power one or more components of the memory device. The second organic substrate may be coupled with the memory device and the first organic substrate. The second organic substrate may include a plurality of second conductive lines arranged with a second pitch smaller than the first pitch and may be configured to route signals between the memory device with a host device.

Memory with fine grain architectures

Methods, systems, and devices for latency offset for frame-based communications are described. A memory system may include a host device and a memory device that communicate using frames based on a frame period of a frame clock. The memory device may receive a read command and a write command from the host device, and determine a read latency and a write latency corresponding to the received commands. The memory device may also determine an additional offset latency to add to the write latency to avoid bus contention between read data and write data associated with the read command and the write command, respectively. The offset latency may correspond to an integer quantity of clock periods, which may be less than the frame period.

Latency offset for frame-based communications

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Boise, ID, United States of America

Brent Keeth