International Business Machines Corporation

Globalfoundries Inc.

Mars, Incorporated

Samsung Electronics Co., Ltd.

Elpis Technologies Inc.

Toshiba America Electronic Components, Inc.

Brent A Anderson

Edward J Nowak

Andres Bryant

Junli Wang

Jed Hickory Rankin

Lawrence Alfred Clevenger

Ruilong Xie

Nicholas Anthony Lanzillo

Albert Manhee Chu

Robert Russell Robison

Kisik Choi

Terence B Hook

Christopher J Penny

William F Clark, Jr

Fee Li Lie

Huiming Bu

John J Ellis-Monaghan

Hemanth Jagannathan

Ruqiang Bao

Choonghyun Lee

Xuefeng Liu

Alain F Loiseau

Kangguo Cheng

Chen Zhang

Stuart A Sieg

Su Chen Fan

Bruce Bennett Doris

Shogo Mochizuki

Balasubramanian Pranatharthiharan

Rajasekhar Venigalla

Anthony K Stamper

Heng Wu

Reinaldo Ariel Vega

Jeffrey Bowman Johnson

Steven J Bentley

Jeffrey P Gambino

Carl John Radens

Dechao Guo

Edmund Juris Sprogis

Chih-Chao Yang

Benjamin David Briggs

Hiroaki Niimi

Herbert Lei Ho

John Edward Barth, Jr

Matthew Joseph Breitwisch

Christopher Joseph Waskiewicz

Tenko Yamashita

Chanro Park

Jeffrey W Sleight

Tak H Ning

Julien Frougier

Sivananda K Kanakasabapathy

James William Adkisson

Mark David Jaffe

Koichi Motoyama

Ravikumar Ramachandran

Robert K Leidy

John Ryan Sporre

Joshua M Rubin

Randy William Mann

Gauri V Karve

Jeanne P Bickford

Indira P Seshadri

Jason D Hibbeler

Juntao Li

David V Horak

Theodorus E Standaert

Josephine B Chang

Vijay Narayanan

Lars W Liebmann

Takeshi Nogami

Soon-Cheon Seo

Christian Lavoie

Kirk David Peterson

Injo Ok

Min Gyu Sung

Paul Stephen Andry

Roy Rongqing Yu

Muthumanickam Sankarapandian

Paul Charles Jamison

Alexander Reznicek

Steven J Holmes

Xin Miao

Ramachandra Divakaruni

Mark Charles Hakey

Mukta G Farooq

Michael A Guillorn

Son Van Nguyen

Michael Rizzolo

Wenyu Xu

Zuoguang Liu

Alvin Jose Joseph

Kerry Bernstein

Subramanian Srikanteswara Iyer

Sanjay C Mehta

Yann Mignot

Wayne Frederick Ellis

Omer H Dokumaci

Robert H Dennard

Richard Quimby Williams

According to the embodiment of the present invention, a semiconductor device includes a first nanodevice and a second nanodevice. The second nanodevice is located adjacent to and parallel to the first nanodevice along a first axis. The first nanodevice and the second nanodevice each include a first section, a second section, and a third section. A first gate cut region is located between the first sections of the first nanodevice and the second nanodevice. A middle gate cut region is located between the second sections of the first nanodevice and the second nanodevice. A third gate cut region is located between the third sections of the first nanodevice and the second nanodevice. The middle gate cut region has different dimensions along a second axis than the first gate cut region and the third gate cut region.

Different dimensions across active region for stronger via to backside power rail

A semiconductor device is provided. The semiconductor device includes a bottom field effect transistor (FET) including a bottom source-drain epitaxial layer formed on sides of the bottom FET; a top FET stacked over the bottom FET; a back-end-of-line (BEOL) layer formed on the top FET; a bottom gate contact formed in contact with the bottom FET and having an extending portion of the bottom gate contact that extends laterally over the bottom source-drain epitaxial layer; and a top gate contact formed in contact with the extending portion of the bottom gate contact and electrically connecting the bottom gate contact to the BEOL layer.

Stacked field effect transistor

A semiconductor structure and method of manufacturing a semiconductor structure having a front side and an opposing backside. An early power delivery network (EBPDN) of wires is built above a substrate layer. Buried power rails (BPRs) are built above levels of the PDN and connected to the EBPDN by short length via connections that can be self-aligned to the back side buried power rails. Both BPRs and vias connections have a common metallization. A front side level of transistor devices are built at the front side of the structure above the BPRs. The resulting formed buried power rail structure has an aspect ratio of height:width greater than 4:1, a height >3 times a height of the formed via structure; and a via structure having a length greater than a height of the formed conductive power rail structure.

Early backside first power delivery network

Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a semiconductor wafer having a first transistor and a second transistor; a first source/drain (S/D) contact of the first transistor; a second S/D contact of the second transistor; and a cut region between the first S/D contact and the second S/D contact, wherein the cut region includes a liner of a first dielectric material and a filler of a second dielectric material that is different from the first dielectric material, the liner lining at least a part of the first S/D contact and a part of the second S/D contact, and the filler being directly adjacent to the liner and between the first S/D contact and the second S/D contact. A method of manufacturing the semiconductor structure is also provided.

Source/drain contact at tight cell boundary

A field effect transistor ('FET') stack, including a lower FET, and an upper FET, a first contact to a lower source drain of the lower FET, a first silicide between the first contact and the lower source drain, the first contact is adjacent to a vertical side surface of the lower source drain, a first overlap region between the first silicide and the first contact is less than a second overlap region between the first silicide and the first source drain. The first contact has a reverse tapper metal stud profile. Forming a first contact to a lower source drain of a lower FET of an FET stack, forming a first silicide between the first contact and the lower source drain, the first contact is adjacent to a vertical side surface of the lower source drain.

Subtractive source drain contact for stacked devices

A microelectronic structure including a first stacked FET device that includes a first bottom FET device and a first upper FET device. The first bottom FET device include a plurality of first bottom channel layers, and the first upper FET device includes a plurality of first upper channel layers. A bottom gate that surrounds the plurality of first bottom channel layers and an upper gate that surrounds the plurality of first upper channel layers. A gate protrusion that extends downwards from the backside of the upper gate to connected to the bottom gate. The gate protrusion partially overlaps with a bottom gate cut region of the first bottom stacked FET device, and the gate protrusion partially overlaps with an upper gate cut region of the first upper stacked FET device.

Stacked FET with extremely small cell height

A microelectronic structure comprises a first interconnect line at a first interconnect level, a second interconnect line at a second interconnect level, and at least one via connecting the first interconnect line at the first interconnect level to the second interconnect line at the second interconnect level. The at least one via comprises a vertical section and at least one horizontal section, the at least one horizontal section being in contact with at least a portion of one of a top surface of the first interconnect line and a bottom surface of the second interconnect line.

Interconnect structures with vias having vertical and horizontal sections

A structure is provided that includes a first metal level including a first metal line, a second metal level spaced apart from the first metal level and including a second metal line, and a first metal via structure connecting the first metal line to the second metal line. The first metal via structure directly contacts a sidewall surface and a horizontal surface of the first metal line.

Wrap around metal via structure

The embodiments herein describe a crossbar VFET where the crossbar channel (or fin) that extends between a pair of channels (fins) has reduced corner rounding, or no corner rounding. This can be achieved by developing a masking feature before etching the channels in the VFET that results in reduced, or no corner rounding in the channel structure etched using the masking feature.

Cross bar vertical FETs

A vertical transport field effect transistor (VTFET) apparatus includes a fin-shaped channel structure; a gate stack that surrounds the channel structure; a top source/drain structure at a top end of the channel structure; a top interconnect layer above the top source/drain structure; a top contact that electrically connects the top source/drain structure to the top interconnect layer; a bottom source/drain structure at a bottom end of the channel structure; a backside interconnect layer below the bottom source/drain structure; and a backside contact that touches a bottom surface of the bottom source/drain structure and also touches a side surface of the bottom source/drain structure and electrically connects the bottom source/drain structure to the backside interconnect layer.

Vertical transport field effect transistor (VTFET) with backside wraparound contact

Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a stack of transistors with a first transistor on top of a second transistor, where a gate of the first transistor has a first width; a gate of the second transistor has a second width; and the first width is narrower than the second width, and where the first and the second transistor respectively have a first gate extension at a first side of the stack and a second gate extension at a second side of the stack, the first gate extension at the first side of the stack being narrower than the second gate extension at the second side of the stack, with the first side being opposite the second side. A method of manufacturing the semiconductor structure is also provided.

Asymmetric gate extension in stacked FET

An approach forming semiconductor structure composed of one or more stacked semiconductor devices that include at least a top semiconductor device, a bottom semiconductor device under the top semiconductor, and contacts to each of the semiconductor devices. The approach provides a stacked semiconductor structure where the bottom semiconductor device is wider than the top semiconductor device. The approach also provides the stacked semiconductor structure where the width of the top semiconductor device is the same as the width of the bottom semiconductor device. The approach includes forming a contact to a side of the bottom semiconductor device when the width of the top semiconductor device is the same as the bottom semiconductor device. The approach includes forming a contact to epitaxy grown on a portion of the top and a side of the bottom semiconductor device when the bottom semiconductor device is larger than the top semiconductor device.

Bottom contact with self-aligned spacer for stacked semiconductor devices

A back side contact structure is provided that directly connects a first electrode of a MRAM, which is present in a back side of a wafer, to a source/drain structure of a transistor. The back side contact is self-aligned to the source/drain structure of the transistor as well as to the first electrode of the MRAM. The close proximity between the MRAM and the source/drain structure increases the speed of the device. MRAM yield is not compromised since no re-sputtering of back side contact metal onto the MRAM occurs.

MRAM integration with self-aligned direct back side contact

A semiconductor structure including a vertical semiconductor channel region, a bottom source drain region arranged on a substrate at a bottom of the vertical semiconductor channel region, a metal gate disposed around the vertical semiconductor channel region, where a first portion of the metal gate extends above the vertical semiconductor channel region, and a gate contact entirely above the vertical semiconductor channel region.

Vertical transistor with reduced cell height

A semiconductor structure having improved performance is provided that includes a local enlarged via-to-backside power rail (VBPR) contact structure which connects a source/drain region of one field effect transistor (FET) to a backside power rail.

Local enlarged via-to-backside power rail

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Jerihco, VT, United States of America

Brent A Anderson