International Business Machines Corporation

Globalfoundries Inc.

Mars, Incorporated

Samsung Electronics Co., Ltd.

Elpis Technologies Inc.

Toshiba America Electronic Components, Inc.

Brent A Anderson

Edward J Nowak

Andres Bryant

Junli Wang

Jed Hickory Rankin

Lawrence Alfred Clevenger

Robert Russell Robison

Terence B Hook

Nicholas Anthony Lanzillo

Kisik Choi

Christopher J Penny

William F Clark, Jr

Ruilong Xie

Albert Manhee Chu

Fee Li Lie

Huiming Bu

John J Ellis-Monaghan

Hemanth Jagannathan

Ruqiang Bao

Choonghyun Lee

Xuefeng Liu

Alain F Loiseau

Kangguo Cheng

Stuart A Sieg

Chen Zhang

Bruce Bennett Doris

Balasubramanian Pranatharthiharan

Rajasekhar Venigalla

Anthony K Stamper

Shogo Mochizuki

Jeffrey Bowman Johnson

Su Chen Fan

Steven J Bentley

Jeffrey P Gambino

Heng Wu

Edmund Juris Sprogis

Chih-Chao Yang

Dechao Guo

Benjamin David Briggs

Hiroaki Niimi

Herbert Lei Ho

John Edward Barth, Jr

Matthew Joseph Breitwisch

Christopher Joseph Waskiewicz

Tenko Yamashita

Chanro Park

Jeffrey W Sleight

Tak H Ning

Julien Frougier

Sivananda K Kanakasabapathy

James William Adkisson

Mark David Jaffe

Robert K Leidy

John Ryan Sporre

Joshua M Rubin

Randy William Mann

Gauri V Karve

Jeanne P Bickford

Jason D Hibbeler

Juntao Li

Carl John Radens

David V Horak

Theodorus E Standaert

Josephine B Chang

Vijay Narayanan

Lars W Liebmann

Takeshi Nogami

Soon-Cheon Seo

Christian Lavoie

Kirk David Peterson

Injo Ok

Min Gyu Sung

Paul Stephen Andry

Roy Rongqing Yu

Koichi Motoyama

Muthumanickam Sankarapandian

Indira P Seshadri

Paul Charles Jamison

Alexander Reznicek

Steven J Holmes

Xin Miao

Ramachandra Divakaruni

Mark Charles Hakey

Mukta G Farooq

Michael A Guillorn

Wenyu Xu

Reinaldo Ariel Vega

Zuoguang Liu

Alvin Jose Joseph

Kerry Bernstein

Subramanian Srikanteswara Iyer

Sanjay C Mehta

Yann Mignot

Ravikumar Ramachandran

Wayne Frederick Ellis

Omer H Dokumaci

Robert H Dennard

Richard Quimby Williams

Anthony I Chou

Johnathan E Faltermeier

A semiconductor device is provided. The semiconductor device includes a field effect transistor (FET) including first and second source/drain (S/D) epitaxial regions. The semiconductor device also includes a gate cut region at cell boundaries between the first and second S/D epitaxial regions, a dielectric liner and a dielectric core formed in the gate cut region, and a backside power rail (BPR) and a backside power distribution network (BSPDN). The semiconductor device also includes a power via passing through the dielectric core and connecting to the BPR and BSPDN, first metal contacts formed in contact with the first and second S/D epitaxial regions, and a via to backside power rail (VBPR) contact. The dielectric liner separates the power via from the first S/D epitaxial region.

Semiconductor device with power via

A top via interconnect with enlarged via top and a fabrication method therefor. One embodiment may comprise a semiconductor interconnect structure, comprising a first dielectric layer having a top surface, a bottom metal line formed in the dielectric layer, a second dielectric layer deposited above the top surface of the first dielectric layer, a via etched through the second dielectric layer above the bottom metal line, wherein the via exposes at least a portion of the top surface of the first dielectric layer, and a metal stud in the via that extends over the exposed at least a portion of the first dielectric layer. The metal stud in the via may further comprise a shoulder surface and a convex top surface.

TopVia interconnect with enlarged via top

A VTFET is on a wafer and a backside power delivery network is on a backside of the wafer. A first backside contact is connected to a gate of the VTFET and a first portion of the backside power delivery network. The VTFET has a first width and the first width is a contacted poly pitch (CPP). The first backside contact may be at least the first width from the VTFET. The first backside contact may be double the first width from the VTFET.

Vertical-transport field-effect transistor with backside gate contact

Embodiments disclosed herein include a semiconductor structure. The semiconductor structure may include a static random access memory (SRAM) cell. The SRAM cell may include a first section of the SRAM cell with a first pull-up transistor, first pull-down transistor, and first pass-gate transistor. The SRAM cell may include a second section of the SRAM cell with a second pull-up transistor, second pull-down transistor, and second pass-gate transistor. The first section of the SRAM cell and the second section of the SRAM cell may be arranged in a non-rectangular cell layout with the first pass-gate located at a first end of the non-rectangular cell layout and the second pass-gate at a second end of the non-rectangular cell layout opposite the first end.

High density stacked vertical transistor static random access memory structure

A plurality of transistor components, a system, and a method of forming a vertically stacked transistor structure within a wafer. The plurality of transistor components may include a first bottom transistor, where the first bottom transistor includes a channel, a gate, a source, and a drain. The plurality of transistor components may also include a first contact on top of the first bottom transistor, where the first contact is proximately connected to the first bottom transistor. The plurality of transistor components may also include a first set of stacked transistors, where the first set of stacked transistors includes a second top transistor on top of a second bottom transistor.

Dummy fin contact in vertically stacked transistors

VFET devices having a robust gate extension structure using late gate extension patterning and self-aligned gate and source/drain region contacts are provided. In one aspect, a VFET device includes: at least one bottom source/drain region present on a substrate; at least one fin disposed on the at least one bottom source/drain region, wherein the at least one fin serves as a vertical fin channel of the VFET device; a gate stack alongside the at least one fin; a gate extension metal adjacent to the gate stack at a base of the at least one fin; a barrier layer that separates the gate extension metal from the gate stack; and at least one top source/drain region at a top of the at least one fin. A VFET device that includes multiple VFETs present on a substrate, and a method of forming a VFET device are also provided.

Late gate extension

A long channel field-effect transistor is incorporated in a semiconductor structure. A semiconductor fin forming a channel region is configured as a loop having an opening therein. A dielectric isolation region is within the opening. Source/drain regions epitaxially grown on fin end portions within the opening are electrically isolated by the isolation region. The source/drain regions, the isolation region and the channel are arranged as a closed loop. The semiconductor structure may further include a short channel, vertical transport field-effect transistor.

Looped long channel field-effect transistor

A semiconductor device includes a first vertical field-effect transistor comprising a first set of vertical fins and a second set of vertical fins separated by a first isolation pillar structure. The semiconductor device further includes a second vertical field-effect transistor adjacent to the first vertical field-effect transistor, the second vertical field-effect transistor comprising a first set of vertical fins and a second set of vertical fins separated by a second isolation pillar structure.

Vertical field-effect transistor with isolation pillars

A semiconductor structure including a first logic cell having a first plurality of nanosheet devices along an axis and a second logic cell having a second plurality of nanosheet devices along the axis. Nanosheets of the second plurality of nanosheet devices are wider than nanosheets of the first plurality of nanosheet devices. The first logic cell is a same type as the second logic cell. The first and second logic cells can include inverter circuits or NAND circuits or NOR circuits. When the first logic cell has a height X, a width Y, and an effective width (W) Z, then the second logic cell has a height 2X, a width Y, and W>2.5 Z.

Staggered stacked circuits with increased effective width

A stacked layer memory for a SRAM includes a first layer of the SRAM, including multiple transistors of a first type, and includes a second layer of the SRAM, having multiple transistors of a second type. The first and second layers are different layers stacked vertically. A width of individual SRAM cells of the stacked layer memory is defined at least by a pitch of a single transistor of the transistors of the first type and the transistors of the second type. A method for forming the stacked layer memory for the SRAM includes forming the first layer and the second layer. The first and second layers are different layers and are formed to be stacked vertically. A width of individual SRAM cells of the stacked layer memory is defined at least by a pitch of a single transistor of the transistors of the first and second types.

Stacked layer memory suitable for SRAM and having a long cell

A semiconductor device is provided that includes at least one stacked FET device including two top transistors stacked over a single bottom transistor. The at least one stacked FET includes a full gate cut structure that is used to separate different device areas from each other, a top gate cut structure that used to separate the two top transistors, and a bottom gate cut structure that is used to provide the single bottom transistor. The at least one FET device can be used to provide a SRAM containing six transistors.

Stacked FET SRAM

Embodiments of present invention provide a transistor structure. The transistor structure includes a first and a second transistor in a first transistor layer; a first and a second transistor in a second transistor layer, respectively, above the first and the second transistor in the first transistor layer; a metal routing layer between the first transistor layer and the second transistor layer; a first local interconnect connecting the first transistor of the first transistor layer to the metal routing layer; and a second local interconnect connecting the metal routing layer to the second transistor of the second transistor layer. A method of manufacturing the transistor structure is also provided.

Local interconnect for cross coupling

A device comprises a first interconnect structure, a second interconnect structure, a first cell comprising a first transistor, a second cell comprising a second transistor, a first contact connecting a source/drain element of the first transistor to the first interconnect structure, and second contact connecting a source/drain element of the second transistor to the second interconnect structure. The first cell is disposed adjacent to the second cell with the first transistor disposed adjacent to the second transistor. The first and second cells are disposed between the first and second interconnect structures.

Backside power rails and power distribution network for density scaling

A channel fin extends vertically above a bottom source/drain region, a protective liner is positioned along opposite sidewalls of the bottom source/drain region. The bottom source/drain region is positioned above a semiconductor layer in contact with a first portion of an inner spacer. A first metal layer is positioned between the first portion of the inner spacer and a second portion of the inner spacer, the first portion of the inner spacer partially covers a top surface of the first metal layer and the second portion of the inner spacer substantially covers a bottom surface of the first metal layer for providing a buried power rail. A shallow trench isolation region is positioned above an exposed portion of the first metal layer, the shallow trench isolation region is adjacent to the first portion of the inner spacer, the semiconductor layer, and the bottom source/drain region.

Buried power rail formation for vertical field effect transistors

A high aspect ratio contact structure formed within a dielectric material includes a top portion and a bottom portion. The top portion of the contact structure includes a tapering profile towards the bottom portion. A first metal stack surrounded by an inner spacer is located within the top portion of the contact structure and a second metal stack is located within the bottom portion of the contact structure. A width of the bottom portion of the contact structure is greater than a minimum width of the top portion of the contact structure.

High aspect ratio contact structure with multiple metal stacks

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Jerihco, VT, United States of America

Brent A Anderson