Cypress Semiconductor Corporation

Enki Technology, Inc.

First Solar, Inc.

Brenor L Brophy

Sina Maghsoodi

Peter R Gonsalves

Ze'ev R Abrams

Marc D Hartranft

Thomas E Colson

Syed Tariq Shafaat

Jeff Hall

Andrew J Wright

Vinod Nair

James H Lie

Yu S Yang

Patrick J Neyman

Kevin Kopczynski

Dinesh Nadavi

Andrew J Walker

Christopher W Jones

Bo Jin

James E Nulty

Thurman John Rodgers

Jeffrey G Hirsch

Mark W Rouse

Niles MacDonald

Kenelm G Murray

Aravamuthan Varadarajan

Qi Gu

Bakul Champaklal Dave

Meisam Movassat

Ramasubrahmaniam Hanumanthu

Xiao Ming Xi

Thomas A McCleary

John O Torode

Disclosed herein are polysilsesquioxane-based anti-reflective coating (ARC) compositions, methods of preparation, and methods of deposition on a substrate. In one embodiment, the polysilsesquioxane of this disclosure is prepared in a two-step process of acid catalyzed hydrolysis of organoalkoxysilane followed by addition of tetralkoxysilane that generates silicone polymers with &#x3e;40 mol % silanol based on Si-NMR. These high silanol siloxane polymers are stable and have a long shelf-life in polar organic solvents at room temperature. Also disclosed are low refractive index ARC made from these compositions with and without additives such as porogens, templates, thermal radical initiator, photo radical initiators, crosslinkers, Si&#x2014;OH condensation catalyst and nano-fillers. Also disclosed are methods and apparatus for applying coatings to flat substrates including substrate pre-treatment processes, coating processes and coating curing processes including skin-curing using hot-air knives. Also disclosed are coating compositions and formulations for highly tunable, durable, highly abrasion-resistant functionalized anti-reflective coatings.

High gain durable anti-reflective coating

Glass coating materials and methods are disclosed for the coating of glass substrates used in the manufacturer of photovoltaic solar modules such that the coating enhances the reliability of the module by reducing its susceptibility to potential induced degradation (PID). Coating materials are disclosed that reduce soiling on the front surface of the glass; that increase the surface resistivity of the glass and that repel moisture and that seal the surface from the ingress of moisture. Further electrically conductive coatings are disclosed that reduce the electric field between the front and back surfaces of the glass and hence reduce ion mobility within the glass and transport from the interior glass surface to the solar cell. There are additional configuration choices for fine tuning associated with separately optimizing the exterior and interior glass coating. Finally, coating processes and methods are disclosed for coating glass substrates with the disclosed materials.

Coating materials and methods for enhanced reliability

Disclosed herein is a coated glass element including a glass component and a coating adhered to the glass component through siloxane linkages, the coating having at least one of an anti-reflective property, a high abrasion resistance property and a hydrophobic property, wherein the coating comprises a dried gel formed from at least one hydrolyzed alkoxysilane-based sol and at least one hydrolyzed organosilane-based sol.

Anti-reflective and anti-soiling coatings with self-cleaning properties

Disclosed herein are single layer transparent coatings with an anti-reflective property, a hydrophobic property, and that are highly abrasion resistant. The single layer transparent coatings contain a plurality of oblate voids. At least 1% of the oblate voids are open to a surface of the single layer transparent coatings.

High gain durable anti-reflective coating with oblate voids

Disclosed herein are coating materials and methods for applying a top-layer coating that is durable, abrasion resistant, highly transparent, hydrophobic, low-friction, moisture-sealing, anti-soiling, and self-cleaning to an existing conventional high temperature anti-reflective coating. The top coat imparts superior durability performance and new properties to the under-laying conventional high temperature anti-reflective coating without reducing the anti-reflectiveness of the coating. Methods and data for optimizing the relative thickness of the under-layer high temperature anti-reflective coating and the top-layer thickness for optimizing optical performance are also disclosed.

Multi-layer coatings

The disclosure discloses abrasion resistant, persistently hydrophobic and oleophobic, anti-reflective and anti-soiling coatings for glass. The coatings described herein have wide application, including for example the front cover glass of solar modules. Methods of applying the coatings using various apparatus are disclosed. Methods for using the coatings in solar energy generation plants to achieve greater energy yield and reduced operations costs are disclosed. Coating materials are formed by combinations of hydrolyzed silane-base precursors through sol-gel processes. Several methods of synthesis and formulation of coating materials are disclosed.

Anti-reflective and anti-soiling coatings for self-cleaning properties

Disclosed is a coating apparatus including flow coating and roll-coating that may be used for uniform sol-gel coating of substrates such as glass, solar panels, windows or part of an electronic display. Also disclosed are methods for substrate preparation, flow coating and roll coating. Lastly, systems and methods for curing sol-gel coatings deposited onto the surface of glass substrates using high temperature air-knives, infrared emitters and direct heat applicators are disclosed.

Coating and curing apparatus and methods

Disclosed are coating apparatus including flow coating and roll-coating that may be used for uniform sol-gel coating of substrates such as glass, solar panels, windows or part of an electronic display. Also disclosed are methods for substrate preparation, flow coating and roll coating. Lastly systems and methods for skin curing sol-gel coatings deposited onto the surface of glass substrates using a high temperature air-knife are disclosed.

Disclosed is a flow coating apparatus, comprising a slot that can dispense a coating material in an approximately uniform manner along a distribution blade that increases uniformity by means of surface tension and transfers the uniform flow of coating material onto an inclined substrate such as for example glass, solar panels, windows or part of an electronic display. Also disclosed is a method of flow coating a substrate using the apparatus such that the substrate is positioned correctly relative to the distribution blade, a pre-wetting step is completed where both the blade and substrate are completed wetted with a pre-wet solution prior to dispensing of the coating material onto the distribution blade from the slot and hence onto the substrate. Thereafter the substrate is removed from the distribution blade and allowed to dry, thereby forming a coating.

Flow coating apparatus and method of coating

In one embodiment, a device is packaged using a low-cost thermally enhanced ball grid array (LCTE-BGA) package. The device may include a die with its backside mounted to the bottom side of a multi-layer packaging substrate. Thermal vias may be formed through the substrate to allow heat to be conducted away from the backside of the die to a top most metal layer of the substrate. Thermal balls may be attached to the bottom side of the substrate on the same plane as the die.

Low cost thermally enhanced semiconductor package

The quality and reliability of electro-optical modules can be improved, for instance, through improved testing and burn-in of an electro-optical sub-assembly. Reliability can also be enhanced through better methods of constructing an electro-optical module. By arranging both an electrical interface and an optical interface on a sub-assembly, for instance, testing can be performed on both interfaces in a single testing process. Burning-in an electro-optical sub-assembly can also improve the reliability of the module by identifying defects. A method of forming an electro-optical module can provide improved reliability by testing and/or burning-in an electro-optical sub-assembly before assembling the module.

Methods of improving reliability of an electro-optical module

Architecture, circuitry, and methods are provided for programming, writing to, or reading from one or more integrated circuits which may be arranged upon a printed circuit board. Programming and read/write operations can, therefore, be done after integrated circuits are populated upon a printed circuit board to control those integrated circuits using a standard JTAG interface, well-known as the IEEE Std. 1149.1 interface. A shift register used to control one or more electronic subcomponents can be programmed, written to, or read from using JTAG programming languages. However, the shift register, or multiple shift registers, used to control electronic subcomponents need not be JTAG compliant. The shift registers may be those found within proprietary circuits, such as analog-to-digital converters or digital-to-analog converters, and include any shift register than receives serial data and produces parallel data, or vice-versa, where the loading and serial shifting of data is controlled using a generic interface, such as enable, reset, capture, etc. One or more shift registers can be distributed among one or more integrated circuits proprietary to the manufacturer of that circuit, and the circuits which embody the shift registers need not have a JTAG interface. Yet, the shift registers can be controlled by a single test access port (TAP) external to the integrated circuits, but which controls the non-JTAG compliant shift registers of each integrated circuit bearing the same. This allows a JTAG programming language which can be readily obtained off-the-shelf to control integrated circuits which do not recognize JTAG control signals, nor do such integrated circuits necessarily have a JTAG four-pin interface.

Architecture, circuitry and method for controlling a subsystem through a JTAG access port

A method of manufacturing a plurality of electro-optical sub-assemblies in parallel is provided. A plurality of printed circuit boards (PCBs) are preferably formed in a panel of flex material. Rigid substrates can be arranged along regions of the PCBs. A plurality of electrical components, including electro-optical semiconductor devices, are preferably located on the rigid substrates. Lens arrays are preferably aligned over the electro-optical semiconductor devices, such as through an alignment mechanism. The PCBs can then be singulated into individual electro-optical sub-assemblies. The rigid substrates can be a plurality of leadframes formed on a matrix leadframe. The matrix leadframe is preferably attached to the panel of flex material such that the leadframes are arranged in proximity to leadframe cutout regions of the PCBs. Electrical interconnections are then preferably formed between the electrical components on the leadframe and the PCBs.

Method of manufacturing electro-optical devices

A system is provided for testing a physical layer device, or various network portions connected to that physical layer device. The test system includes a random bit generator that, during use, produces a random pattern of bits clocked in parallel onto the transmit portion of the physical device. The parallel-fed information can then be serialized and selectably fed back to the receive input of the same physical device. The receive portion of the physical device can then deserialize the random pattern of bits, and present those bits to logic within the test system. The test system can, therefore, compare each of the random pattern of bits presented to the physical device with corresponding bits derived from the deserializer. If each bit within the random pattern of m bits forwarded to the serializer does not compare with each corresponding m bits forwarded from the deserializer, then the physical device is known to be a failure. Instructions which begin and end the test operation are forwarded from a test device that is linked to the test system by a JTAG access port configured according to IEEE Std. 1149.1. This allows non-proprietary instructions to be sent into the access port controller, using only a single input pin among the four-pin JTAG access port, where a decoder within the test system is programmed to decode that instruction and either begin or end the test operation. A clock generation circuit will generate a high speed clock, for use by the physical device, to allow the physical device to operate at speed without requiring a costly test system to generate a high-speed clock and signals proprietary to that test system.

Growing community of inventors

San Jose, CA, United States of America

Brenor L Brophy