Cadence Design Systems, Inc.

Breno Rodrigues Guimaraes

Fabiano Cruz Peixoto

Lawrence Loh

Lars Lundgren

Andrea Iabrudi Tavares

Matheus Nogueira Fonseca

Xiaoyang Sun

Thamara Karen Cunha Andrade

Artur Melo Mota Costa

Claudionor Coelho, Jr

Habeeb Farah

Vaibhav Mittal

Andreas Tiemeyer

Aspects are directed to formal verification of computer instructions. A system may present, at a user interface, a first model including one or more instructions, the first model corresponding to a data structure that corresponds to the instructions in the first model, obtain, via the user interface and during a first traversal of the data structure, a first indication to modify to a predetermined value an unmodified parameter of an instruction among the instructions, and present, at the user interface in response to the indication to modify the unmodified parameter, a second indication of execution of one or more of the instructions in an order according to a second model that corresponds to the data structure and based on a modified parameter.

User interface for formal verification of computer instructions for compatibility with a compiler architecture

This disclosure relates to signal observability rating. In an example, a method can include propagating a clock signal through a respective module of a circuit design in a forward and backward direction, evaluating clock signal propagation results for the respective module based on a forward and backward clock signal propagation of the clock signal to compute an observability rating for a data signal to be processed by the respective module during formal verification, and updating a current observability rating of the respective property for the data signal to the computed observability rating.

Systems and methods for signal observability rating

Disclosed are techniques for verifying an electronic design using hierarchical clock domain crossing verification techniques. These techniques identify an electronic design including a top hierarchy and one or more instances at a first child hierarchy below the top hierarchy. The electronic design may be decomposed into a top hierarchy block for the top hierarchy and one or more child blocks for the one or more instances. A plurality of data structures may be generated by separately processing the top hierarchy block and the one or more child blocks on one or more computing nodes. One or more clock domain crossing structures may be identified in the electronic design at least by integrating the plurality of data structures.

Methods, systems, and articles of manufacture for verifying an electronic design using hierarchical clock domain crossing verification techniques

A method for data propagation analysis. A data propagation diagram for a circuit design is generated. The data propagation diagram includes a plurality of nodes and a plurality of edges connecting the nodes. The nodes represent data locations in the circuit design and the edges represent data propagation paths between the data locations in the circuit design. A signal trace specifying signal values for the circuit design is analyzed to determine whether data at a first data location of the data locations during a first clock cycle is causally related to the data at a second data location of the data locations during a second clock cycle. A visual animation is displayed on the data propagation diagram indicating movement of the data between a first node of the nodes corresponding to the first data location and a second node of the nodes corresponding to the second data location.

Data propagation analysis for debugging a circuit design

Growing community of inventors

Minas Gerais, Brazil

Breno Rodrigues Guimaraes