Cadence Design Systems, Inc.

Breno Rodrigues Guimarães

Fabiano Cruz Peixoto

Björn Håkan Hjort

Abner Luis Panho Marciano

Caio Araujo Teixeira Campos

The present disclosure relates to a method for electronic design verification. Embodiments may include receiving, using a processor, at least one electronic design file and a set of inputs from a user, wherein the at least one electronic design file and set of inputs are associated with an electronic design. Embodiments may further include performing formal verification on at least a portion of the electronic design and determining, using a model checker, one or more conflicts associated with a variable during the formal verification. Embodiments may also include translating the one or more conflicts into one or more corresponding signal names and displaying, at a graphical user interface, the corresponding signal names.

System, method, and computer program product for providing feedback during formal verification

Disclosed are techniques for enhancing formal verification with counter acceleration for electronic designs. These techniques identify at least a portion of an electronic design including a counter having a current counter value and intercept next counter values transmitted to the counter with a counter abstraction module. These techniques further determine whether to accelerate the counter from the current counter value to an engine synthesized next counter value, rather than to an original next counter value based at least in part on a set of critical values. The counter is accelerated from the current counter value to the engine synthesized next counter value when the counter abstraction module determines to accelerate the counter.

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Belo Horizonte, Brazil

Breno Rodrigues Guimarães