Advanced Micro Devices Corporation

Other

Semicaps Pte Ltd

Brennan V Davis

Michael R Bruce

Rosalinda M Ring

Jeffrey David Birdsley

Rama Rao Goruganthu

Daniel L Stone

Glen P Gilfeather

Victoria Jean Bruce

David Harry Eppes

Srikar V Chunduri

Miguel Santana, Jr

Choon Meng Chua

Lian Ser Koh

Soon Huat Tan

Robert Powell

Jiann Min Chin

Gregory A Dabney

Richard Jacob Wilcox

Thomas Chu

Palaniappan Muthupalaniappan

Jacob Phang

Hoo-Yin Ng

The invention is directed to a system and method for analyzing an integrated circuit having silicon on insulator (SOI) structure. According to one example embodiment of the present invention, an optical beam arrangement is adapted to direct a modulated beam at a selected portion of the integrated circuit. The beam is sufficiently modulated to inhibit optical beam intrusion on the structure and operation of the integrated circuit. A reflected optical waveform response is obtained from the SOI selected portion. The inhibition of optical beam intrusion enhances the ability to analyze integrated circuits using an optical beam, making possible the use of analysis methods that otherwise would be difficult or even impossible to use.

Optical analysis of integrated circuits

Apparatus for and methods of inspection using laser beam induced alteration are provided. In one aspect, an apparatus is provided that includes a laser scanning microscope for directing a laser beam at a circuit structure and a source for biasing and thereby establishing a power condition in the circuit structure. A detection circuit is provided for detecting a change in the power condition in response to illumination of the circuit structure by the laser beam and generating a first output signal based on the detected change. A signal processor is provided for processing the first output signal and generating a second output signal based thereon. A control system is operable to scan the laser beam according to a pattern that has a plurality of pixel locations, whereby the laser beam may be moved to a given pixel location and allowed to dwell there for a selected time before being moved to another pixel location.

Laser beam induced phenomena detection

Analysis of a semiconductor die is enhanced by the stimulation the die and the detection of a response to the stimulation. According to an example embodiment of the present invention, a semiconductor die is analyzed using indirect stimulation of a portion of the die, and detecting a response therefrom. First, selected portion of circuitry within the die is stimulated. The stimulation of the selected portion induces a second portion of circuitry within the die to generate an external emission. The emission is detected and the die is analyzed therefrom. In one particular implementation, a response from the selected portion is inhibited from interfering with the detection of the emission from the second portion of circuitry.

Indirect stimulation of an integrated circuit die

The present invention is directed analysis of a flip-chip integrated circuit die having SOI structure that improves the ability to image and analyze selected portions of circuitry in the die. According to an example embodiment of the present invention, a lens is formed in a back side of a flip-chip die and over the insulator portion of SOI structure in the die. Light is directed at the lens and the lens is used to focus the light to target circuitry in the die. A reflection from the circuitry is detected and used to analyze the die, such as by imaging the circuitry in the die and identifying defects therein. The lens formed in the die enhances the ability to focus light to selected circuitry in the die and improves the ability to analyze dies having SOI structure through the insulator.

IC die analysis via back side lens

Semiconductor analysis is improved via the use of fiber optic communications. According to an example embodiment of the present invention, a stimulation device is adapted to stimulate an integrated circuit die, and the die generates a response to the stimulation. An optical signal generator, either incorporated into the die or coupled to the die, detects the response, converts the response to an optical signal and transmits the optical signal. The optical signal is received at a testing arrangement adapted to analyze the die therefrom. The optical signal is used to analyze the die, improving signal quality and the ability to perform high-speed analysis of the die.

Semiconductor die analysis via fiber optic communication

The operability of light-based semiconductor die analysis is enhanced using a method and arrangement that directs light between a light source and a die. In one example embodiment of the present invention, a light source is directed to a die in a semiconductor analysis arrangement using a fiber optic cable. The analysis arrangement is adapted to use light received via the fiber optic cable to analyze the die. The analysis includes one or more light-based applications, such as stimulating a selected portion of the die with the light and detecting a response therefrom. In this manner, light can be directed to a die in a variety of analysis implementations, such as for analyzing a die in a test chamber.

Fiber optic semiconductor analysis arrangement and method therefor

Various methods of hot-electron imaging a workpiece are provided. In one aspect, a method of examining a workpiece is provided that includes directing a first photon at a photodetector at a first known time and stimulating a circuit device of the workpiece at a second known time to produce a condition in the circuit device conducive to photon emission. At least one photon emitted by the circuit device in response to the stimulation is detected. The first photon increases the quantum efficiency of the photodetector in detecting the at least one photon. The detection of the at least one photon relative to the first known time and the second known time is time correlated to temporally distinguish the first photon and the at least one photon and to temporally correlate the stimulation of the circuit device to the detection of the at least one photon.

Photon detection enhancement of superconducting hot-electron photodetectors

According to an example embodiment of the present invention, a portion of substrate in the back side of a semiconductor chip is removed as a function of photons emitted through substrate remaining at the back side. The use of emitted photons is used to control the substrate removal process.

Substrate removal as a function of emitted photons at the back side of a semiconductor chip

Post-manufacturing analysis of a semiconductor chip is enhanced via a method and system for viewing emissions through substrate in the back side of the chip. According to an example embodiment of the present invention, a portion of circuitry in a semiconductor chip is excited, and an emission is generated. An optical microscope is directed at the backside of the chip, and an image of the emission is obtained. The optical microscope is coupled to an indium-gallium-arsenic (InGaAs) camera that is used to detect the emission. In this manner, emissions can be detected through substrate in a semiconductor chip.

Real-time photoemission detection system

The operability of light-based semiconductor die analysis is enhanced using a method and arrangement that can detect light leakage between a light source and a die. In one example embodiment of the present invention, a light source is directed to a semiconductor analysis arrangement using, for example, a fiber optic cable. The analysis arrangement is adapted to use light from the light source for analyzing the die. A light detection arrangement detects a condition of light leakage from the system and generates a signal representing the condition of light leakage. The generated signal can then be used to control the semiconductor analysis arrangement, such as by deactivating the light source in response to a detected leak, or by allowing the light source to function in response to not detecting a leak.

Semiconductor analysis arrangement and method therefor

According to an example embodiment of the present invention, a defect detection approach involves detecting the existence of defects in an integrated circuit as a function of at least one applied energy source. In response to energy that is applied to the integrated circuit, response signals are detected. A parameter including information such as amplitude, frequency, phase, or a spectrum is developed for a reference integrated circuit device and then compared to the detected response signal. The deviation in the response and reference signals, and the type of energy source used, are correlated to a particular defect in the device.

Defect detection in semiconductor devices

Semiconductor die analysis is enhanced using a system that is adapted to perturb a die in a test chamber and to detect a response from the die to the perturbation. According to an example embodiment of the present invention, a semiconductor die analysis system includes a test chamber and a docking arrangement adapted to dock with the test chamber. A die is held in the docking arrangement and is presented inside of the test chamber when the docking arrangement is docked with the chamber. Two or more perturbation devices are used to perturb the die, and controller is adapted to control the perturbation. A data acquisition arrangement receives data from the die in response to the perturbation, and the data is used for analyzing the die.

Analysis of a semiconductor die having silicon-on-insulator (SOI) structure is enhanced by accessing the circuitry within die from the back side without breaching the thin insulator layer of the SOI structure. According to an example embodiment, a portion of substrate is removed from the back side of a semiconductor die having a SOI structure and a backside opposite circuitry in a circuit side. Electrical connection is made to a portion of the circuitry within the die via a capacitive coupling arrangement. The electrical connection is used to obtain an electrical measurement correlated with circuitry logic states of the die that is used for analysis.

SOI die analysis of circuitry logic states via coupling through the insulator

Semiconductor analysis is enhanced using a system and method for improving the heat-dissipation characteristics of a semiconductor die. According to an example embodiment of the present invention, a flip-chip integrated circuit die having circuitry in a circuit side opposite a back side is formed having a back side including a thermal conductivity enhancing material. The thermal conductivity enhancing material improves the heat dissipating characteristics of the die during operation and testing and helps to reduce or prevent overheating. An epitaxial layer of silicon is formed in the back side, and circuitry is constructed in the epitaxial layer. Pre-existing circuitry on the circuit side and the newly formed circuitry in the back side are electrically coupled. The back side circuitry is operated in conjunction with the circuit side circuitry during testing and operation, and is useful, for example, for replacing defective circuitry, modifying circuit operation, and/or providing stimuli to the circuit side circuitry. The thermal conductivity enhancing material dissipates the heat generated by the circuitry and reduces the risk of a thermal related breakdown of the die. This improves the ability to analyze the die under normal and above normal operating temperatures without necessarily causing a failure in the die.

IC die analysis via back side circuit construction with heat dissipation

A method for detecting substrate damage in a flip chip die, having a back side and a circuit side, that uses magnetic resonance imaging. The back side of the die is first globally thinned down and a region for examination is selected. A magnetic field is applied to the selected region and then the region is scanned with a magnetic resonance imaging arrangement. A plurality of perturbations are measured to generate an array of perturbation signals, which are then converted to a local susceptibility map of the selected region of the die. The susceptibility map of the selected region is then examined to determine if there is any substrate damage.

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Austin, TX, United States of America

Brennan V Davis