Intel Corporation

Fei Comapny

Brennan Peterson

Kevin Fischer

Vinay B Chikarmane

Stacey Stone

Michael Schmidt

Richard J Young

Steven W Johnston

Jeff Blackwood

Michael Moriarty

Rudolf Johannes Peter Gerardus Schampers

Craig Henry

Kerry L Spurgin

Guus Das

Larry Dworkin

Paul Keady

Ruud Schampers

A method for TEM sample preparation and analysis that can be used in a FIB-SEM system without re-welds, unloads, user handling of the lamella, or a motorized flip stage. The method allows a dual beam FIB-SEM system with a typical tilt stage to be used to extract a sample to from a substrate, mount the sample onto a TEM sample holder capable of tilting, thin the sample using FIB milling, and rotate the sample so that the sample face is perpendicular to an electron column for STEM imaging.

High throughput TEM preparation processes and hardware for backside thinning of cross-sectional view lamella

A method for Transmission Electron Microscopy (TEM) sample creation. The use of a Scanning Electron Microscope (SEM)&#x2014;Scanning Transmission Electron Microscope (STEM) detector in the dual-beam focused ion beam (FIB)/SEM allows a sample to be thinned using the FIB, while the STEM signal is used to monitor sample thickness. A preferred embodiment of the present invention can measure the thickness of or create TEM and STEM samples by using a precise endpoint detection method. Preferred embodiments also enable automatic endpointing during TEM lamella creation and provide users with direct feedback on sample thickness during manual thinning. Preferred embodiments of the present invention thus provide methods for endpointing sample thinning and methods to partially or fully automate endpointing.

Measurement and endpointing of sample thickness

A method for forming a slot contact structure for transistor performance enhancement. A contact opening is formed to expose a contact region, and a slot contact is disposed within the contact opening in order to induce a stress on an adjacent channel region. In an embodiment, a stress inducing barrier plug is disposed within a portion of the contact opening and the remainder of the contact opening is filled with a lower resistivity contact metal. By selecting the proper materials and deposition parameters, the slot contact can be tuned to induce a tensile or compressive stress on the adjacent channel region, thus being applicable for both p-type and n-type devices.

Stressed barrier plug slot contact structure for transistor performance enhancement

A method for Transmission Electron Microscopy (TEM) sample creation. The use of a Scanning Electron Microscope (SEM)&#x2014;Scanning Transmission Electron Microscope (STEM) detector in the dual-beam focused ion beam (FIB)/SEM allows a sample to be thinned using the FIB, while the STEM signal is used to monitor sample thickness. A preferred embodiment of the present invention can measure the thickness of or create TEM samples by using a precise endpoint detection method. Preferred embodiments also enable automatic endpointing during TEM lamella creation and provide users with direct feedback on sample thickness during manual thinning. Preferred embodiments of the present invention thus provide methods for endpointing sample thinning and methods to partially or fully automate endpointing.

Embodiments of barriers to use in semiconductor devices are presented herein.

Barrier formation and structure to use in semiconductor devices

A method for forming a slot contact structure for n-type transistor performance enhancement. A slot contact opening is formed to expose a contact region, and a barrier plug is disposed within a portion of the slot contact opening in order to induce a tensile stress on an adjacent channel region. The remainder of the slot contact opening is filled with a lower resistivity contact metal. Barrier plug deposition temperature can be varied in order to tune the tensile stress on the adjacent channel region.

Tuned tensile stress low resistivity slot contact structure for n-type transistor performance enhancement

Apparatus and methods of fabricating an atomic layer deposited tantalum containing adhesion layer within at least one dielectric material in the formation of a metal, wherein the atomic layer deposition tantalum containing adhesion layer is sufficiently thin to minimize contact resistance and maximize the total cross-sectional area of metal, including but not limited to tungsten, within the contact.

Atomic layer deposited tantalum containing adhesion layer

Copper interconnects may be made using the damascene process with reduced copper corrosion. Copper corrosion may be reduced by planarizing through excess copper down to, but not completely through, a copper diffusion barrier layer. The copper diffusion barrier layer may be removed using a different technique. Thereafter, suitable chemicals may be utilized to clean the structure.

Reducing corrosion in copper damascene processes

A barrier architecture is provided that includes different materials that are selected to be employed in connection with copper contact applications. Some of the barrier material is formed over trench contact sidewalls, and other different barrier material is formed over trench contact bottoms. By selecting the appropriate barrier materials, electromigration can be improved while, at the same time, interconnect and contact resistances can be kept low and array leakage can be mitigated.

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Portland, OR, United States of America

Brennan Peterson