Texas Instruments Corporation

Brendan Walsh

Richard D Simpson

Karl M Guttag

Philip John Moyse

Laura Dudbridge

David Collins

A three input arithmetic logic unit (230) forms a mixed arithmetic and Boolean combination of three multibit input signals. The arithmetic logic unit (230) first forms a Boolean combination and then forms an arithmetic combination. The current instruction drives an instruction decoder (250, 245) that generates the functions signals F0-F7 which control the combination formed. The three input arithmetic logic unit (230) preferably employs a set of bit circuits (400), each forming carry propagate, generate and kill signals. These signals may employed with a multilevel logic tree circuit and a carry input to produce a bit resultant and a carry output to the next bit circuit. This structure permits formation of selected arithmetic, Boolean or mixed arithmetic and Boolean function of the three input signals based upon the current instruction. Selection of the function signals enables the combination to be insensitive to one of the input signals, thus performs a two input function of remaining input signals. The instruction itself may include the function signals and function modification bits, or the function signals and function modification signals may be stored in a special data register. Function modification signals cause modification of the function signals prior to use. The three input arithmetic logic unit (230) includes a least significant bit carry-in generator (246) supplying a carry input to the least significant bit. This carry input is determined by the combination being formed, and generally is '1' only during subtraction. The carry input may be specified in the special purpose data register (D0) for certain instructions. The combination formed is optionally modified dependent upon the sign bit of one of the inputs.

Three input arithmetic logic unit forming mixed arithmetic and boolean

A three input arithmetic logic unit (230) forms a mixed arithmetic and Boolean combination of three multibit input signals. The current instruction drives an instruction decoder (250, 245) that generates functions signals F0-F7 which control the combination formed. The three input arithmetic logic unit (230) preferably employs a set of bit circuits (400), each forming carry propagate, generate and kill signals. These signals and a carry input produce a bit resultant and a carry output to the next bit circuit. Selection of the function signals enables the combination to be insensitive to one of the input signals, thus performing a two input function of remaining input signals. The instruction itself may include the function signals and function modification bits, or the function signals and function modification signals may be stored in a special data register. Function modification signals cause modification of the function signals prior to use. The three input arithmetic logic unit (230) includes a least significant bit carry-in generator (246) supplying a carry input to the least significant bit circuit (400). This carry input is determined by the combination being formed, and generally is '1' only during subtraction. The carry input may be specified in the special purpose data register (D0) for certain instructions.

Three input arithmetic logic unit employing carry propagate logic

Three input arithmetic logic unit forming the sum of a first input anded

A three input arithmetic logic unit (230) forms a mixed arithmetic and Boolean combination of three multibit input signals. The arithmetic logic unit (230) first forms a Boolean combination and then forms an arithmetic combination. The current instruction drives an instruction decoder (250, 245) that generates the functions signals F0-F7 which control the combination formed. The arithmetic logic unit (230) includes a first three input Boolean function generator (496) forming a Boolean combination F1(A,B,C), a second three input Boolean function generator (497) forming a Boolean combination F2(A,B,C), and an adder (495) forming the sum of the two Boolean combinations. The first Boolean combination F1(A,B,C) and the second Boolean combination F2(A,B,C) are independently selected from the set of all possible Boolean combinations of three multibit input signals A, B and C. The adder (495) includes a least significant bit carry-in generator (246) supplying a carry input to the least significant bit. This carry input is determined by the combination being formed, and generally is '1' only during subtraction.

Three input arithmetic logic unit forming the sum of a first Boolean

Apparatus for detecting the leftmost '1' bit or the rightmost '1' bit of an input number includes a binary tree (11) of two-inputs OR-gates (13, 14, 15, 16) or their logical equivalent to which the input number is applied in parallel and from which signals are derived and applied as inputs and to control a plurality of trees (MA, MB, MC) of two-input multiplexers (12) from the outputs (E0, E1, E2, E3) of which appear the bits of a number representing the position in the input number of the leftmost '1' or the rightmost '1' bit.

Growing community of inventors

Bedford, United Kingdom

Brendan Walsh