Advanced Micro Devices Corporation

University of Alaska

Brendan J Babb

Frank W Moore

Steven B Sidman

Methods and systems for processing data are disclosed. An example method can comprise receiving first data. The method can comprise applying a first transform to the first data. The first transform can be evolved from a second transform. The first transform can be based on first coefficients and the second transform can be based on second coefficients. The first transform can be evolved without constraining a count of the first coefficients to be equal to a count of the second coefficients. The method can comprise providing the transformed first data.

Evolved transform for processing data

A manipulated error detection matrix by which check bits are generated and decoded so that errors that are detected are next to each other and occur within a nibble. The invention consists of a check bit generator 14 which generates check bits in accordance with a nibble protect matrix according to a Modified Hamming Code which is configured to provide detection of triple and quadruple bit errors occurring within a nibble. The check bits are compared to those in memory 12 by a syndrome generator 16. An error corrector 18 and an error detector 20 decode syndrome bits.

Error detection and correction circuit

The present invention addresses the need in the art by providing a novel approach to the correction of errors in check bits in an encoded data word. The invention consists of a check bit output latch 16 which stores check bits generated by a check bit generator 14 and outputs the newly generated check bits to memory 12 when a single error occurs in the word located in the check bits. The data is corrected so the newly generated check bits are correct and can be latched out to memory 12 at the same time the data is latched out. The invention includes a syndrome generator 18, an error corrector 34, and an error detector 36. The present invention provides a powerful performance boost to error detection and correction circuits by correcting check bits in memory with newly generated check bits when no errors in the data word are detected.

The present invention (10) substantially overcomes many of the problems associated with prior art error detection codes by providing a novel approach to detecting and correcting multiple bit errors. The invention (10) organizes the data word into a matrix of n by m bits, where n is the number of m bit groups. Parity bits are generated for each column and each row and used to detect single, double and triple bit errors.

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Anchorage, AK, United States of America

Brendan J Babb