Xilinx, Inc.

Brendan Farley

John E McGrath

Woon Wong

Christophe Erdmann

Bruno Miguel Vaz

John G O'Dwyer

Paul Newson

Bob W Verbruggen

John Edward Mcgrath

John K Jennings

Roberto Pelliconi

Conrado K Mesadri

Ali Boumaalif

Darragh Walsh

Gamal Refai-Ahmed

Suresh Ramalingam

Matthew H Klein

Edward Cullen

Ionut C Cical

Anthony J Collins

Declan Carey

Anthony Torza

Chi-Yi Chao

James Hudner

Ivan Bogue

Marc Erett

Christopher Erdman

Jens Weis

Lik Tsang

John G O′Dwyer

An example programmable device includes a configuration memory configured to store configuration data; a programmable logic having a configurable functionality based on the configuration data in the configuration memory; a signal conversion circuit; a digital processing circuit; an endpoint circuit coupled to the signal conversion circuit through the digital processing circuit; wherein the digital processing circuit includes a first one or more digital processing functions implemented as hardened circuits each having a predetermined functionality, and a second one or more processing functions implemented by the configurable functionality of the programmable logic.

Programmable device having hardened circuits for predetermined digital signal processing functionality

Systems and methods for monitoring a number of operating conditions of a programmable device are disclosed. In some implementations, the system may include a root monitor including circuitry configured to generate a reference voltage, a plurality of sensors and satellite monitors distributed across the programmable device, and a interconnect system coupled to the root monitor and to each of the plurality of satellite monitors. Each of the satellite monitors may be in a vicinity of and coupled to a corresponding one of the plurality of sensors via a local interconnect. The interconnect system may include one or more analog channels configured to distribute the reference voltage to each of the plurality of satellite monitors, and may include one or more digital channels configured to selectively route digital data from each of the plurality of satellite monitors to the root monitor as data packets.

Root monitoring on an FPGA using satellite ADCs

An antenna assembly is provided having passive cooling elements that enable compact design. In one example, an antenna assembly is provided that includes a heat sink assembly having an interior side and an exterior side, an antenna array, an antenna circuit board, and a radome. The antenna circuit board includes at least one integrated circuit (IC) die. The IC die has a conductive primary heat dissipation path to the interior side of the heat sink assembly. The radome is coupled to the heat sink assembly and encloses the antenna circuit board and the antenna array between the radome and the heat sink assembly. The heat sink assembly includes a metal base plate and at least a first heat pipe embedded with the metal base plate. The first heat pipe is disposed between the metal base plate and the IC die.

Radome with integrated passive cooling

A radar system includes a transmitter to transmit a sequence of pulses, a receiver to receive reflections of the transmitted pulses, and velocity detection circuitry to determine a velocity of an object in a path of the transmitted pulses based at least in part on the transmitted pulses and the reflected pulses. The transmitter includes a plurality of digital-to-analog converters (DACs) to generate the sequence of pulses in response to a clock signal. The receiver includes a plurality of analog-to-digital converters (ADCs) to sample the reflected pulses in response to the clock signal. Accordingly, the ADCs are locked in phase with the DACs.

Phase noise compensation in digital beamforming radar systems

Method and apparatus for monitoring and reconfiguring a programmable device are disclosed. In some implementations, the programmable device may include a processor and a plurality of satellite monitors to determine operating temperatures at various locations throughout the programmable device. When temperatures of at least some of the satellite monitors exceed a threshold, the processor may reconfigure the programmable device using an alternative configuration. The alternative configuration may provide equivalent functionality with respect to an initial configuration through a different arrangement of functional blocks within the programmable device. The new arrangement of functional blocks may reduce operating temperatures by relocating blocks to different regions of the programmable device.

Thermal load balancing of programmable devices

Examples described herein provide for a relaxation oscillator and corresponding methods of operation. In an example, a circuit includes a dynamically controllable current source, a capacitor, and an oscillator generation circuit. The dynamically controllable current source includes a digitally tunable current mirror configured to generate a current. The digitally tunable current mirror includes multiple transistors configured to be selectively electrically connected in parallel to alter a gain of the digitally tunable current mirror to control the current. The capacitor is selectively electrically connected to the dynamically controllable current source. The oscillator generation circuit is electrically connected to the capacitor. The oscillator generation circuit is configured to generate an oscillation signal in response to a voltage of the capacitor.

Relaxation oscillator having a dynamically controllable current source

Apparatus and associated methods relate to maintaining a total current of a switch cell in a digital-to-analog converter at a controllable operating point by adjusting shunt current control signals applied to programmable shunt current sources in opposite polarity with respect to a tail current control signal applied to a programmable tail current source. In an illustrative example, the total current may flow through differential legs of a switch cell. The programmable shunt current sources may, for example, be configured to compensate for adjustments to the programmable tail current source. In an illustrative example, tail current and shunt currents may flow through a pair of cascode transistors. In various examples, controlling the programmable shunt current sources to compensate adjustments to the tail current source may, for example, permit controlled common mode voltage or operating point so as to reduce device voltage stress over a wider dynamic range of output voltages.

Embedded variable output power (VOP) in a current steering digital-to-analog converter

An integrated circuit is described. The integrated circuit comprises an analog-to-digital converter circuit configured to receive an input signal at an input and generate an output signal at an output; and a monitor circuit coupled to the output of the analog-to-digital converter circuit, the monitor circuit configured to receive the output signal and to generate integration coefficients for the analog-to-digital converter circuit; wherein the integration coefficients are dynamically generated based upon signal characteristics of the output signal generated by the analog-to-digital converter circuit. A method of receiving data in an integrated circuit is also described.

Circuit for and method of receiving data in an integrated circuit

Apparatus and associated methods relating to a digital-to-analog converter (DAC) include a programmable resistance network coupled between a voltage supply node Vand a switch cell circuit to provide a predetermined resistance in response to the Vand current Iof the switch cell circuit. In an illustrative example, the DAC may include a switch cell circuit comprising one or more switch cells connected in parallel. Each switch cell may include a differential gain circuit having a first branch coupled to a second branch at an input of a current source. The programmable resistance may include a variable resistance configured to adjust a voltage (Vbias) supplied to the switch cell circuit in response to a control signal. By introducing the programmable resistance network, predetermined bias and/or gain values may be dynamically adjusted with a constant board-level power supply V.

Embedded variable gain amplifier in a current steering digital-to-analog converter

An analog-to-digital converter (ADC) circuit () and method of operation are disclosed. In some aspects, the ADC circuit () may include a plurality of channels (), a gain calibration circuit (), and a time-skew calibration circuit (). Each of the plurality of channels () may include an ADC (), a switch () configured to provide a differential input signal to the ADC (), a calibration device (), a multiplier (), and a pseudorandom bit sequence (PRBS) circuit () to provide a pseudorandom number (PN) to the switch (), to the calibration device (), and to the multiplier (). In some embodiments, the calibration device () may include first and second offset calibration circuits (-) coupled in parallel between a de-multiplexer (D) and a multiplexer (M) that alternately route signals to the first and second offset calibration circuits (-) based on the pseudorandom number (PN).

Circuit to calibrate chopping switch mismatch in time interleaved analog-to-digital converter

Disclosed approaches for limiting use or a programmable IC involve a provider of programmable ICs generating, using one or more private keys of the provider, one or more signed configuration bitstreams from one or more circuit designs received from a customer. The provider changes the general purpose programmable IC into an application programmable IC that can only be programmed by the one or more signed configuration bitstreams. The application programmable IC and the one or more signed configuration bitstreams are provided from the provider to the customer.

Growing community of inventors

Donabate, Ireland

Brendan Farley