Intersil Americas Inc.

Cirrus Logic Inc.

Brannon Craig Harris

Travis Guthrie

James R Toker

Narendra Kayathi

Douglas R Holberg

Sunder S Kidambi

David R Welland

Caiyi Wang

Michael P Anthony

Nadi Rafik Itani

Sandra Marie Johnson

Alan Wayne Hansford

Syed Khalid Azim

Ash Prabala

Shih-chung Chao

A current measurement circuit may include unbuffered inputs, and the current may be sampled directly from the input pins. The input current created from each sample may be cancelled by injecting opposite charge on the subsequent sample. This direct sampling from the pins increases the common mode input range of the sense path without having to build high linearity rail-to-rail input buffers, hence lowering cost and power consumption of the current measurement path. It also allows for high-impedance input sampling. The measurement circuit may include multiple sampling stages, with a first sampling stage implemented as a switched-capacitor based circuit. A compensator circuit coupled in a feedback loop from the output of the first sampling stage to the input pins may be operated to provide the equivalent charge back to the input pins every cycle to cancel the input current required to charge the sampling capacitors of the first sampling stage.

Input current compensation during current measurement

An adjustable current-synthesizer may generate synthesized current representative of an actual current, according to a model of a circuit that produces the actual current. The current synthesizer may under-sample a current sense signal derived from the actual current to obtain a few samples of the actual current, which are then used to adjust the synthesized current, thereby ensuring accuracy of the synthesized current. Sample values of the actual current are compared with corresponding generated values of the synthesized current to obtain offset values. In order to maintain monotonicity in the synthesizer results, the offset values are used to make adjustments to the slope of the synthesized current. The slope of the synthesized current may also be adjusted according to the slope of the actual current. Sub-Nyquist sampling of the actual current may be performed on the down-slope, with up-slope adjustments made based on the offset adjustment and down-slope adjustment.

Current synthesizer correction

Techniques for the estimation of sample-time and gain mismatch errors in a two-channel time interleaved analog to digital converter that are devoid of any multiplication operation. In a sample-time mismatch error evaluation, the signs and the absolute values from the two ADCs are used to provide an estimate of the sample-time mismatch error. In a gain error estimation algorithm, the absolute values of the outputs from the two ADCs are subtracted and accumulated. The errors can then be corrected, in a preferred embodiment, using suitable adaptive sample time and gain correction techniques.

Multiplier-free algorithms for sample-time and gain mismatch error estimation in a two-channel time-interleaved analog-to-digital converter

A wide band analog-to-digital converter used in a frequency multiplexed communication system. The converter includes a plurality, M, of time-interleaved analog-to-digital converter subunits (ADC subunits). The sampling rate, FS, of the M ADC subunits is selected to locate one or more integer multiples of a Nyquist frequency of a respective subunit ADC in one or more guard bands, and/or such that one or more integer multiples of FSare also located in the guard bands.

Sampling method for time-interleaved data converters in frequency-multiplexed communications systems

An image processor system for a charge coupled device (CCD) or CMOS imaging system includes a correlated double sample and variable gain (CDSVGA) circuit for receiving data from a CCD system and an automatic gain control (AGC) circuit which first controls gain by adjusting said CCD system and then for yet a higher gain level makes gain adjustments in said CDSVGA circuit AND a digital gain circuit to produce a combined target gain level. A processing system for an imager device includes a camera system for producing an imager signal, a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA), an analog-to-digital converter (ADC) coupled to said CDS circuit, a digital gain circuit (DGC) coupled to said ADC, and an automatic gain control (AGC) circuit coupled to said DGC for controlling the CDS circuit and the DGC. The processing circuitry includes an analog front end and a digital signal processing system for capturing full motion video and outputting a CCIR 601 4:2:2 YCrCb video data output for presentation on a user selected display.

Correlated double sampling variable gain amplifier circuit for use in a digital camera

The method of mounting a semiconductor device,on a supporting structure,, the semiconductor device having a surface,including a defined area,for receiving photons and a plurality of conductors,for establishing connections to the device. An aperture,is formed through the supporting structure, the aperture sized to correspond to a size of the defined area of the semiconductor device. Conductors,are formed on the supporting structure adjacent to the aperture in a pattern corresponding to the pattern of the conductors on the semiconductor device. The semiconductor device is mounted to the supporting structure such that the conductors on the semiconductor device contact the conductors on the supporting structure where the defined area of the semiconductor device is exposed to photons through the aperture.

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Austin, TX, United States of America

Brannon Craig Harris