Heartbeam, Inc.

Intel Corporation

Newcardio, Inc.

Branislav Vajdic

Ljupco Hadzievski

Bosko Bojovic

Marjan Miletic

Dorin Panescu

Vladan Vukcevic

Uros Mitrovic

Stephen L Smith

Alexander D Lunginovic

Gregory E Atwood

Neal R Mielke

Owen W Jungroth

Petra Belicev

Vladimir Atanasoski

Goran Gligoric

Bosko Vulicevic

Compact, mobile three-lead cardiac monitoring devices for remote detection and/or diagnosis of cardiac events (e.g., acute myocardial infarction). The apparatus may include two integrated hand electrodes and two chest electrodes disposed on two pivotable arms that are capable of retracting in the compartments, enabling a compact size when the device is not used. Also described herein are systems including these devices and methods of using them.

Compact mobile three-lead cardiac monitoring device

Wrist-wearable apparatuses that may be removed and used as a chest-applied cardiac device may include two chest electrodes on an inner surface of a strap (or strap regions), as well as two finger or more finger electrodes on the opposite side of the apparatus. The apparatus may be removed from the wrist and placed on a chest of a patient such that two electrodes are spaced at least five centimeters apart and in contact with the chest and held in place with two or more fingers to capture orthogonal cardiac signals that may be synthesized into a conventional 12-lead cardiac signal.

Apparatus for generating an electrocardiogram

Methods and apparatuses, including devices and systems, for remote and detection and/or diagnosis of acute myocardial infarction (AMI). In particular, described herein are handheld and adhesive devices having an electrode configuration capable of recording three orthogonal ECG lead signals in an orientation-specific manner, and transmitting these signals to a processor. The processor may be remote or local, and it may automatically or semi-automatically detect AMI, atrial fibrillation or other heart disorders based on the analyses of the deviation of the recorded 3 cardiac signals with respect to previously stored baseline recordings.

Electrocardiogram patch devices and methods

Systems and apparatus for synthesizing (generating) 12-lead ECG dataset from 3-lead ECG data. In particular, one or more transformation parameters may be determined that may be applied to 3-lead ECG dataset to generate 12-lead ECG data with particular speed and accuracy. The transformation parameters, which may include a plurality of matrices, may be determined from a synchronized patient's 12-lead ECG dataset and 3-lead ECG data. The 12-lead ECG dataset may be collected at a different time than the 3-lead ECG data. In some embodiments, the 12-lead ECG dataset and/or the 3-lead ECG dataset may be resampled prior to determining the transformation parameters.

Method and apparatus for reconstructing electrocardiogram (ECG) data

Method and apparatus for computer enabled analysis of ECG (electro cardiographic) data by exploiting computerized three-dimensional spatial presentation of the measured data using vectors. A three-dimensional presentation of the human heart may be correlated with waveforms specific for standard ECG or derived ECG signals based on the dipole approximation of the heart electrical activity. Additional tools for analyzing ECG data are also provided which may be used to determine the time of cardiac electrical events, to select specific beats for automated cardiac interval determination, and to flag ECGs that have been evaluated by automated means but may benefit by human reading.

Method and apparatus for quantitative assessment of cardiac electrical events

A reference scheme for verifying the erasing and programming in an electrically erasable and electrically programmable read-only memory fabricated on a silicon substrate which employs a plurality of memory cells, each of which contains a floating gate. The reference scheme employs trimmable single cell reference devices for both the erase verify and program verify operations. The threshold voltages of the reference cells are trimmed to a level below (in the case of the erase verify reference cell) or above (in the case of the program verify reference cell) which all memory cells in the array will be considered in a particular program state (i.e., erased or programmed). In the case of the read reference device, a double-cell read referencing device combining the erase and program verify reference cells is described. Although, the double-cell referencing device is preferred, a trimmable read reference device is also taught.

Single cell reference scheme for flash memory sensing and program state

A circuit for controlling substrate bias voltage of a MOS semiconductor substrate. A first level detector monitors the substrate voltage and when the substrate bias falls below a threshold value, the first level detector couples an oscillator to cause a charge pump to pump charges into the substrate until the threshold level is again reached. A second detector operates as an excess negative voltage detector. This second detector monitors the substrate and when the bias voltage exceeds a predetermined limit, the second detector activates a clamper which drives the substrate toward ground potential until the bias voltage is again under the predetermined limit. By this technique the substrate bias is kept between the first threshold level and the maximum limit level. The first and second detectors are comprised of two transistor circuits, wherein the first leg is comprised of a depletion transistor and at least one enhancement transistor coupled between the supply voltage and the substrate. The second leg is comprised of two depletion transistors coupled between the supply voltage and its return. The junction of the depletion and the enhancement transistor of the first leg is coupled to the gate of one of the depletion transistors in the second leg such that the second leg is biased by the voltage on the junction of the transistors of the first leg which monitors the substrate voltage. The two legs determine the activation point of the detectors. The second detector is made to have at least one more enhancement transistor than the first detector to establish the limit level to be above that of the threshold level.

Stable substrate bias generator for MOS circuits

A current controlled switch to compensate for switching time variations. A compensated current source is configured to operate with a current mirror to set the switching current. The control of the switching current maintains control of the peak switching current in the switch, therein controlling the switching transition time. The speed performance is maintained nearly uniform as circuit and process variations cause switching conditions to change. Applications such as delay lines, output buffers, inverters and ringing oscillators are available using the current controlled switching technique of the present invention. Also, parasitic effects can also be compensated by using the present invention.

Current controlled solid state switch

A current difference current source which provides a stable current as operating conditions change. Two MOS transistors operate as two current sources. A difference current is obtained by subtracting the two transistor currents. The two current sources are configured to vary similarly as conditions change, such that their difference remains constant. In the alternative the difference current is forced to decrease as current increases in the transistors, wherein a reverse compensated current is provided. The difference current is used to drive a current mirror which functions as a compensated current source.

Growing community of inventors

Los Gatos, CA, United States of America

Branislav Vajdic