Lsi Corporation

Brandon L Hunt

Jeffrey K Whitt

Luke Everett McKay

Lakshmana M Anupindi

Moby J Abraham

Edoardo Daelli

Sreedeepti Reddy

Michael S Fry

Methods and structure for enabling re-training of a DDR memory controller in a storage device without loss of data in the DDR memory devices of the cache memory in response to detecting failure of the memory subsystem during operation of the storage device. In response to detecting a failure of the memory subsystem, the memory controller is reset without resetting the memory devices. The memory controller is then re-trained for operation with the memory device. During the re-training, self-refresh mode of the memory devices is disabled and manual refresh is performed by a processor of the storage device to thereby retain any user data in the memory device.

Methods and structure to assure data integrity in a storage device cache in the presence of intermittent failures of cache memory subsystem

A method for robust preamble location and gate training in a Double Data Rate type Three (DDR3) computing environment. A single algorithm is employed to begin sampling a Data Strobe Signal (DQS) at a maximum delay value designed to fall within the driven region of a DQS. The method then begins sampling the DQS in a sequence of delay values from right to left. Each result of the sampling indicating a high state and a low state are stored as well as the occasions where the DQS transitioned from high to low indicating a rising edge. At a consecutive number of samples returning a low state, the method determines the preamble has been reached and discontinues sampling. The method retains the most recently stored rising edge as the first rising edge and configures the result for gate training.

Method for robust preamble location in a DQS signal

A method for detecting a failure in a serial topology. The method may comprise sending a predetermined pattern to a plurality of devices communicatively connected to an initiator in a serial topology; receiving a return result from each of the plurality of devices in response to the predetermined pattern; recognizing a problem associated with a particular device among the plurality of devices, the problem being recognized based on the return result from the particular device; sending a plurality of test patterns to the particular device; receiving a plurality of test results from the particular device in response to the plurality of test patterns; and determining a cause of the problem based on the plurality of test results, the cause of the problem being at least one of: a cable failure and a device failure.

Method for detecting a failure in a SAS/SATA topology

A method for training an electronic memory may include receiving a first delay value and a second delay value. The first delay value and the second delay value may be associated with a first data strobe indicating when to sample data on a first memory lane of the electronic memory. The method may also include determining a difference between the first delay value and the second delay value. The method may further include receiving a third delay value associated with a second data strobe indicating when to sample data on a second memory lane of the electronic memory. The method may also include determining a fourth delay value for the second memory lane of the electronic memory utilizing the third delay value and the determined difference between the first delay value and the second delay value.

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Colorado Springs, CO, United States of America

Brandon L Hunt