International Business Machines Corporation

Brandon Edward Schenck

Steven Michael Douskey

Michael John Hamilton

Matthew Roger Ellavsky

Dong Chen

Alan G Gara

Martin Ohmacht

Thomas M Gooding

Mark James Jeanson

Gerard Vincent Kopcsay

Ryan Andrew Fitch

Rudolf Adriaan Haring

Timothy D Helvey

Don Darrell Reed

Richard A Swetz

Thomas A Liebsch

Sean T Evans

Bradley Craig White

Daniel J Littrell

Jason L Van Vreede

Ross L Franke

A method, system and computer program product are provided for implementing enhanced net routing for congestion resolution of non-rectangular or rectangular hierarchical macro designs of an integrated circuit chip. Congested macro nets near a macro boundary are identified. Wiring channels are reserved outside the macro boundary, allowing congested macro nets to be routed outside the physical boundary of the macro while still being logically contained within the macro.

Implementing enhanced net routing congestion resolution of non-rectangular or rectangular hierarchical macros

A circuit generates a global clock signal with a pulse width modification to synchronize processors in a parallel computing system. The circuit may include a hardware module and a clock splitter. The hardware module may generate a clock signal and performs a pulse width modification on the clock signal. The pulse width modification changes a pulse width within a clock period in the clock signal. The clock splitter may distribute the pulse width modified clock signal to a plurality of processors in the parallel computing system.

Global synchronization of parallel processors using clock pulse width modulation

An adaptation of standard boundary cell architecture defined by the IEEE 1149.1 Joint Test Action Group (JTAG) interface standard to provide paths to functional circuitry via the re-use of JTAG standard test data registers (TDR) and interface. Existing multi-core processor solutions are covered, but an expansion for a more generic solution is provided. In general, an integrated circuit is provided with a plurality of function registers along with a plurality of I/O units. The I/O units are arranged in a serial communications chain located around the boundary of the integrated circuit's functional circuitry. Each of the I/O units include JTAG standard serial TDR in serial communication with adjacent I/O units. Moreover, each I/O unit includes JTAG standard parallel TDR that is associated with and in parallel communication with the I/O unit's JTAG standard serial TDR. Further still, a digital logic interface is configured to control the direct transfer of data between the JTAG standard parallel TDR and a corresponding one of the plurality of function registers. As a result of the re-use of existing boundary scan architecture, a significant reduction in wiring congestion is realized. Thus, asynchronous communication is provided without sacrificing valuable integrated circuit real estate.

Asynchronous communication using standard boundary architecture cells

An adaptation of a test data register (TDR) structure defined by the IEEE 1149.1 Joint Tag Action Group (JTAG) interface standard to provide a debugging path. Existing multi-core processor solutions are covered, but an expansion for a more generic solution is provided. In general, the present apparatus is for extending the IEEE 1149.1 JTAG standard to provide an asynchronous protocol for bypassing test circuitry and bi-directionally communicating with functional circuitry. The apparatus includes an integrated circuit having function register and JTAG standard TDR. Digital logic is configured to control the direct transfer of data between the JTAG standard TDR and the function register.

Asynchronous communication apparatus using JTAG test data registers

In a method of generating clock signals for a level-sensitive scan design latch, at least one test input signal is transmitted to a plurality of splitter leaves. Once the test input signal is stabilized at each of the splitter leaves, generating a shaped oscillator clock signal having a predetermined pattern of pulses from a central root is generated. At the plurality of splitter leaves, the test input signal is logically combined with the shaped oscillator clock signal, thereby generating a first latch clock signal and a second latch clock signal. The logically combining action includes applying a delay of less than one clock cycle to the shaped oscillator clock signal to generate a delayed oscillator clock signal; logically combining the delayed oscillator clock signal with a second signal so as to generate the first latch clock signal; and logically combining the shaped oscillator clock signal with a third signal so as to generate the second latch clock signal.

Self-test design methodology and technique for root-gated clocking structure

Growing community of inventors

Rochester, MN, United States of America

Brandon Edward Schenck