Xilinx, Inc.

Google Inc.

Brandon Blodget

Scott P McMillan

Prasanna Sundararajan

Philip Bryn James-Roxby

Patrick Lysaght

Adam P Donlin

Eric R Keller

Michael Peter Thompson

Cameron D Patterson

William Marlyan Carey

Zebedee Pedersen

Jayme Ross Goldstein

Ted Larson

Stavros Vranakis

Alexandra Maria Fernandes De Castro

Hana Tanimura

Iain Roberts

Nicholas Inzucchi

Paulo Blikstein

Joao Henrique Santos Wilbert

Derek R Curd

Stephen Andrew Neuendorffer

Delon Levi

Paul M Hartke

Richard J LeBlanc

Tobias J Becker

Punit S Kalra

Vincent P Eck

Bernard J New

Robert D Turney

Paul R Schumacher

Peter H Alfke

Steven A Guccione

Carl H Carmichael

Mark Paluszkiewicz

Arnan Sipitakiat

Hayden Kwok-Hay So

Nicholas P Sedcole

Systems and methods associated for providing haptic feedback are provided. For instance, data indicative of a feedback scheme associated with an input mechanism can be accessed. The feedback scheme includes one or more feedback points associated with a position of a moveable portion of the input mechanism. The input mechanism is configured to change positions responsive to an actuation of the input mechanism by a user. One or more positions of the moveable portion of the input mechanism can be determined as the input mechanism is actuated by the user. Operation of one or more feedback motors can be controlled to provide feedback to the user in accordance with the feedback scheme based at least in part on the determined one or more positions of the input mechanism.

Haptic feedback system

Systems and methods associated with modular computing environments are provided. For instance, a modular computing environment can include a control entity including one or more processing devices. The modular computing environment can include one or more modular components directly or indirectly coupled to the control entity. The one or more modular components can be configured to receive a module specifying one or more instructions to be performed by an external device. The one or more modular components include one or more processing devices. Each modular component is configured to determine state data associated with the modular component based at least in part on the received module and to provide the state data to the control entity. The state data includes an identification signature of the received module and a configuration context of the modular component within the modular computing environment.

Modular computing environment

A top-level directory of a virtual file system is created. A hierarchy of directories is created under the top-level directory including creating a first file that contains an architecture description of the multi-device circuit arrangement. The directories have names indicative of the plurality of devices and configurable resources of the plurality of devices of the architecture description specified in the first file. A first set of one or more files is created that contain state data or configuration data for configuring resources of the plurality of devices to perform functions specified by the configuration data. A mapping of the configuration data to the resources of the plurality of devices is determined, and configuration data is stored in the configurable resources according to the mapping.

Configuration of a large-scale reconfigurable computing arrangement using a virtual file system interface

Various approaches for controlling a circuit implemented on an integrated circuit device having programmable logic. According to one approach a hierarchy of directories and files are maintained in a virtual file system that is registered with an operating system. The directories and files are associated with resources of the programmable logic. Each file represents a respective data set of configuration data for an associated one of the resources, and at least one of the files is a clock control file that is associated with a clock control circuit on the integrated circuit. A first value is stored in the clock control circuit of the programmable logic in response to invocation of an operating system file access command that references the clock control file and specifies the first value. Advancement of a clock signal on the programmable logic is controlled in response to the first value stored in the clock control circuit.

Debugging using a virtual file system interface

Method and apparatus for encoding configuration data is described. An integrated circuit device having a configuration interface is coupled to boot memory coupled at the configuration interface. The boot memory contains boot cores for configuring the integrated circuit device via the configuration interface. The boot cores include a configuration encoder core and an internal processor interface core. The boot cores may further include a processor core. The configuration encoder core provides a peripheral interface internal to the integrated circuit device, and the boot memory contains at least one set of instructions for encoding configuration data read from configuration memory. The encoded configuration data may be sent via the peripheral interface. Alternatively, configuration encoder core may include a configuration bitstream for instantiating an encoder in configurable resources for encoding readback configuration data.

Bootable integrated circuit device for readback encoding of configuration data

Enhancing relocatability of partial configuration bitstreams from a first area to a second area of programmable logic of an integrated circuit is described. A first set and a second set of logic resources of the programmable logic are identified. The first set and the second set of logic resources are respectively associated with the first area and the second area, the second area being wholly or partially offset from the first area. Differences between the first set of logic resources and the second set of logic resources are identified. The differences are associated with one or more of different types of circuit resources in each of the first area and the second area. Prohibit constraints associated with the differences are set.

Enhancing relocatability of partial configuration bitstreams

A method for instantiating a design in programmable logic of an integrated circuit is described. First configuration information is generated for configuration of the static portion of the design. The first configuration information includes routing information for routing static routes of the static portion of the design using interconnect lines. Second configuration information is generated for configuration of the at least one dynamic portion of the design. The first configuration information and the second configuration information are merged to provide third configuration information, the third configuration information being for configuration of the at least one module in the programmable logic.

Modular partial reconfiguration

Approaches for validating a configuration bitstream used for partially reconfiguring an ingrated circuit such as a programmable logic device (PLD) are disclosed. In one approach, the integrated circuit is configured with a first configuration bitstream that includes first bit values that produce an implementation of a static part of a design on the integrated circuit. Any differences between a bit value in a second configuration bitstream and a corresponding bit value of the implementation of the static part of the design are determined. The second configuration bitstream includes second bit values that produce an implementation of a reconfigurable part of the design on the integrated circuit. A first signal state is output in response to determining that there are no differences, and a second signal state is output in response to determining that there are differences.

Validating partial reconfiguration of an integrated circuit

A method and apparatus for accessing internal registers of hardware blocks in a programmable logic device (PLD) are described. An aspect of the invention relates to a method of accessing at least one internal register of a hardware block in a PLD. The PLD is actively reconfigured with a first partial bitstream to sever first connections between input/output (IO) pins of the hardware block and a user design, and establish second connections between the IO pins and state access logic. The at least one internal register is accessed using the state access logic. The PLD is actively reconfigured with a second partial bitstream to establish third connections between the IO pins and the user design.

Method and apparatus for accessing internal registers of hardware blocks in a programmable logic device

Various approaches for embedding identifier information in a configuration bitstream for a programmable logic device (PLD) are disclosed. In various embodiments, the bits in the configuration bitstream that are unused in implementing a the design are identified. The identifier information is encrypted, and a subset of the unused bits are selected using a pseudo-random function. The encrypted identifier information is placed in the selected subset of unused bits. Decryption is accomplished by reversing the encryption approach.

Concealed, non-intrusive watermarks for configuration bitstreams

Methods and apparatus are described for providing access to data in a programmable logic device (PLD). A hierarchy of directories and files are maintained in a virtual file system, which is registered with an operating system. The directories and files are associated with resources of a PLD. In response to program calls to file system routines that reference files associated with resources of the PLD, the virtual file system is invoked, and the virtual file system accesses state information in resources of the PLD.

Virtual file system interface to configuration data of a PLD

A method and system are disclosed. The method and system provide the ability to identify a configuration bit as an essential configuration bit. The identifying that is performed uses a configuration bit definition.

Method and system for identifying essential configuration bits

A method and system for generating a bitstream view of a programmable logic device (PLD) design are disclosed. The present invention allows for the correlation of a physical circuit description (e.g., one or more of a PLD design's essential configuration bits) and a logical circuit description (e.g., one or more of the logic elements that make up a PLD design), which can also be viewed as correlating one or more of the physical elements of the design's implementation in the PLD with one or more of the design's logical elements.

Method and system for generating a bitstream view of a design

A programmably configurable logic-based macro is described. Portions of configuration logic blocks for interconnectivity are assigned. The portions are configured as respective shift registers. Interconnects are routed between design static locations associated to provide interconnectivity between the portions. The portions assigned and routed are saved as a macro file. Inputs and outputs of the macro file are defined in a hardware description language. The hardware description language definition of the inputs and the outputs of the macro file are synthesized to provide a bitstream for programming programmably configurable logic associated with the portions. A shift register-to-shift register module interface boundary is created within an array of the programmably configurable logic.

Growing community of inventors

Santa Clara, CA, United States of America

Brandon Blodget