Emc Corporation

Dell Products Inc.

Brandon Barney

Steven D Sardella

Robert P Wierzbicki

Ralph C Frangioso, Jr

Douglas Sullivan

Stephen William Daniel

James Marriott Guyer

Michael John Kozel

Jay J Davis

Kenneth M Sullivan

Darrin Haug

Richard John Boyle

Damian Dayton

Jeffrey A Moore

James H Street

Renee J Walker

Andrew Wrobel

A folding pillow includes a top pillow section and a bottom pillow section. The top pillow section includes a first access opening, and a first internal pillow insert. The bottom pillow section includes a second access opening, and a second internal pillow insert. The folding pillow also includes a hinge section, where the folding pillow is configured to fold at the hinge section and have a folded position and an unfold position. The folding pillow also includes a sleeping panel, where the sleeping panel is covered when the folding pillow is in the folded position.

Folding pillow

In one or more embodiments, one or more systems, one or more methods, and/or one or more processes may determine that a platform reset signal from a processor of an information handling system has been asserted; may determine that a power conservation state from the processor was not asserted within an amount of time; may determine that an operating system restart occurred; may notify a hardware root of trust device to authenticate information handling system firmware; may assert a resume reset signal to the processor; may authenticate the information handling system firmware; may de-assert a power OK signal to the processor; may remove power from the processor; may determine that the resume reset signal to the processor is de-asserted and that the processor is out of the power conservation state; and may provide power to the processor.

System and method of operating an information handling system

Described is an electronics enclosure having a midplane, a first field-replaceable CPU (central processing unit) module, and a second field-replaceable CPU module. Each CPU module is independently pluggable into and removable from the midplane. Each CPU module is configurable into either one of a first configuration and a second configuration, wherein the CPU modules operate independently as separate CPU modules when configured according to the first configuration and cooperate as a unitary CPU module when configured according to the second configuration.

Scalable CPU (central processing unit) modules for enabling in-place upgrades of electronics systems

An apparatus for protecting electronic equipment from voltage surges includes a network interface coupled to a computer device for connecting the computer device to a computer network and a discrete voltage surge protection device coupled to the computer network with a first unshielded cable and to the network interface with a second unshielded cable. The unshielded cable comprises at least one wire pair and the discrete protection device comprises a voltage suppressor device coupled between the wires of each wire pair. The discrete voltage surge protection device renders the apparatus compliant with the Telcordia (Bellcore) GR-1089-CORE Intrabuilding Lightning Surge Tests.

System for protecting computer equipment from lightning voltage surges

A test module is provided for testing system modules. All the test circuitry and test connectors reside on the test module. The test module is coupled to the system modules during testing, and is removed from the system after testing. Test connectors and test circuitry on the test module support such test functions as voltage margining, CPU emulation, and JTAG boundary scanning. A JTAG selection function can also be provided for selecting one or more JTAG loops for testing individually or as a single loop. The test module further includes level shifters for converting between 3.3V and 1.2V.

Test module for testing of electronic systems

Boards in a system are interconnected by a first set of signals including a first control signal and first function signals. Each board in the system includes a second set of signals corresponding to the first set of signals. When the first control signal and a first function signal are asserted, the corresponding second signals of are asserted in response and a function is performed on the boards. But, if any of the second signals are asserted, none of the first signals is asserted in response. Test signals on boards are thereby isolated from test signals coupled to all the boards on the system, so a fault on any signal in any second set of signals will not propagate to the first set of signals.

Highly available system test mechanism

A circuit board has a first signal layer having a set of conductors, a second signal layer having a conductive plane and a non-conductive region, and a third signal layer having a conductive region that mirrors the non-conductive region of the second signal layer. The circuit board further includes a first separating layer having non-conductive material which is disposed between the first signal layer and the second signal layer, and a second separating layer having non-conductive material which is disposed between the second signal layer and the third signal layer. Accordingly, traces within the first signal layer and overlying the conductive plane of the second signal layer will have a first impedance, while traces within the first signal layer and overlying the non-conductive region of the second signal layer and the conductive region of the third signal layer will have a second impedance that is different than the first impedance.

Techniques for making a circuit board with improved impedance characteristics

A computer system for managing a computer network comprises a rack cabinet having a cabinet interior. A plurality of infrastructure connector assemblies are fixedly mounted on the rack cabinet in 1-U boundaries, each infrastructure connector assembly including a signal snap interface connector and a power snap interface connector. A plurality of compute elements are adapted to be slidably disposed within the cabinet interior of the rack cabinet in a stacked relationship, each compute element including at least one infrastructure connector assembly which releasably snap-interconnects with an associated infrastructure connector assembly mounted on the rack cabinet. A distributed power bay is disposed within the rack cabinet and provides central power for the computer system. A rack manager is disposed within the rack cabinet and includes the central video and I/O devices for the computer system. A cabinet controller is disposed within the rack cabinet and is responsible for the management of a geography bus and an intelligent chassis management bus for the computer system.

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Hudson, MA, United States of America

Brandon Barney