Avago Technologies General IP (singapore) Pte. Ltd.

Brady A Koenig

Jason Todd Gentry

Richard S Rodgers

Stephen Dixon

An embodiment of a method for register placement in an integrated circuit (IC) includes determining a data path between circuit elements, placing at least one register along the data path, performing a static timing analysis on the data path, extracting top-level timing data to develop an extended timing path, the extended timing path comprising a plurality of timing path segments; processing the top-level timing data to determine whether the extended timing path violates a timing requirement, and moving the at least one register along the data path to satisfy the timing requirement if the timing requirement is violated.

System and method for automatic timing-based register placement and register location adjustment in an integrated circuit (IC)

A floor planning tool is provided that performs the functions that are typically performed by floor planning tools, but in addition, determines the supply of routing resources and the demand on routing resources for all routing channels while applying variable routing rules and static timing estimations to arrive at a preliminary routed floor plan. This drastically reduces the number of iterations that subsequently will need to be performed by the floor planning tool and by routing and static timing analysis tools to arrive at a final routed floor plan.

Computer system and method for performing a routing supply and demand analysis during the floor planning stage of an integrated circuit design process

Differences between block interfaces of a partitioned logic block in two floorplans of an integrated circuit can be determined by comparing an image of pins of a partitioned logic block in a first floorplan of the integrated circuit with an image of pins of the partitioned logic block in a second floorplan of the integrated circuit. The second floorplan can represent a new floorplan design resulting from a change to an integrated circuit design represented by the first floorplan. If no differences exist between pins of the partitioned logic block in the first and second floorplans, information representing the partitioned logic block in the second floorplan can be substituted with information representing the partitioned logic block in the first floorplan.

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Fort Collins, CO, United States of America

Brady A Koenig