Intel Corporation

Intel Corportion

Bradly L Inman

James Edward Neeb

Nathan S Blackwell

Christopher J Nelson

Timothy J Callahan

Stephen Sturges

Shelby G Rollins

Sundar V Pathy

Matthew Hendricks

Hiren V Tilala

Jared Pager

Embodiments herein relate to apparatus, systems, and methods to compress a test pattern onto a field programmable gate array to test a device under test. This may include identifying values of a plurality of drive pins for a plurality of test cycles to apply to an input of the DUT for each of the plurality of test cycles, identifying values of a plurality of compare pins for the plurality of test cycles to compare an output of the DUT, respectively, for each of the plurality of test cycles, analyzing the identified values, compressing, based on the analysis, the values of the plurality of drive pins and the plurality of compare pins, and storing the compressed values on the FPGA.

Compressed test patterns for a field programmable gate array

Techniques and configurations are disclosed herein for communication between devices. In some embodiments, a bus for communication between first and second devices may include a transmit buffer and one or more processing devices. The one or more processing devices may be configured to receive first asynchronous data from an operating system, running on a central processing unit of the first device, on an operating system signal path; transmit the first asynchronous data from the first device to the second device on a command signal path; transmit first data from the transmit buffer to the second device at a first fixed packet frequency on a transmit signal path; and receive data from the second device at a second fixed packet frequency on a receive signal path different from the transmit signal path. Other embodiments may be disclosed and/or claimed.

Bus for communication between devices

Asynchronous communication between devices

An automatic method and apparatus in a computer system of cache detection. Accessing of data stored at first specified boundaries in a memory of the computer system corresponding with a first size of a cache is timed to produce a first timing value. Accessing of data stored at second specified boundaries in the memory of the computer system corresponding with a second size of a cache which is greater than the first size is timed to produce a second timing value. If the second timing value exceeds the first timing value by a threshold then the presence of a cache of the first size is indicated. This can also be performed iteratively until the memory of computer system has been completely tested for the presence of any caches. The process may be performed for instruction or data caches wherein the accessing of data for data caches includes memory access instruction, and the accessing of data for instruction caches includes the execution of instructions. Methods and apparatus for determining other cache characteristics are also described including detecting the set associativity of any known caches, and whether the known data and instruction caches are unified or not.

Cache detection using timing differences

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Hillsboro, OR, United States of America

Bradly L Inman