Hewlett-packard Company

Bradly J Foster

Steven J Kommrusch

S Paul Tucker

David J Hodge

A computer graphics system includes an apparatus for fog blending colors to be displayed on a graphics display of the computer graphics system. The computer graphics system includes a rendering parameter calculation unit responsive to data of a primitive, that determines a cooked exponent value and a color value for at least one pixel of the primitive. In addition, the system includes a fog unit responsive to the cooked exponent value for each pixel of the primitive, that determines a fog blending factor for each pixel of the primitive, wherein the fog blending factor is one of an exponential fog blending factor and an exponential-squared fog blending factor. Further, the system includes a fog blending unit responsive to the color value and the fog blending factor for each pixel of the primitive and also to a fog color value, that blends the fog color value with the color value for each pixel of the primitive according to the fog blending factor for the respective pixel, and that provides a fogged color value for each pixel of the primitive. In addition, the computer graphics system may include a first interpolator, responsive to the color value and the cooked exponent value for at least one pixel of the primitive, that determines the color value and the cooked exponent value along an edge of the primitive so as to provide the cooked exponent value and the color value for each pixel of the edge of the primitive. Further, the computer graphics system may also include a second interpolator, responsive to the cooked exponent value and the color value for each pixel of the edge of the primitive, that determines the cooked exponent value and the color value along a span of the primitive so as to provide the cooked exponent value and the color value for each pixel of the span of the primitive. In this way, the system provides fast and accurate exponential and exponential-squared fog blending of the color values of the primitive without a lot of hardware.

Computer graphics system having per pixel fog blending

Data values representative of a source image are processed with a dither matrix having dither values corresponding to pixel locations in the source image. The dither matrix has dimensions n.times.n, where n is modulo 4 and an integer value m exists such that m.multidot.m=n. The dither matrix is typically a 4.times.4 matrix. The dither values are arranged in the dither matrix such that each row, column, diagonal and m.times.m submatrix in the dither matrix adds to substantially the same value, preferably the sum of all dither values in the dither matrix divided by n. A dither value corresponding to a pixel location is accessed in the dither matrix. An initial data value associated with the pixel location is combined with the accessed dither value, typically by adding, to provide an intermediate value. The intermediate value is clamped and truncated to provide a dithered data value. Where each pixel is represented by two or more data values, such as color values, a dither matrix is associated with each parameter. Preferably, the sum of the selected dither matrices is a matrix having matrix values that are substantially the same.

Methods and apparatus for processing data values representative of an

A dot clock generation system has a voltage-controlled oscillator (VCO) for generating a dot clock signal for an analog-to-digital convertor (ADC). A dot clock synchronization (sync) generator counts cycles of the dot clock signal and generates a dot clock sync signal. An analog video signal is passed through a first differential buffer to create an analog video sync signal. The analog video sync signal is passed through a first flip-flop storage element to a phase detector. The dot clock sync signal is passed through a second storage element and then through a second differential buffer to the phase detector. The second storage buffer insures that the edge of the dot clock sync signal which is used by the phase detector is tightly tied with the sampling edge of the dot clock signal which is used by the ADC to sample the analog data within the analog video signal. Moreover, the first and second buffers and storage elements introduce similar propagation time delays into the analog video sync signal and the dot clock sync signal. Accordingly, the phase detector accurately compares the phases of these sync signals and generates a highly accurate voltage control signal for the voltage-controlled oscillator, thereby resulting in a high precision dot clock signal.

Dot clock generation with minimal clock skew

A synchronization (sync) separation system and method quickly and accurately generate a sync signal from an analog video signal by using feedback control. The system comprises a voltage generator for generating first and second reference voltages V.sub.REF1, V.sub.REF2. A first comparator compares the analog video signal to the first reference voltage V.sub.REF1 and generates a shift control signal, A voltage shift mechanism receives the shift control signal and adjusts the analog video signal so that the sync level of the analog video signal converges toward the first reference voltage V.sub.REF1. A second comparator compares the analog video signal with the second reference voltage V.sub.REF2 and generates the sync signal indicative of when the analog video signal exhibits the sync level. Preferably, the voltage shift mechanism introduces a continuous current i.sub.c into the analog video signal. Moreover, the second comparator is an ECL differential line receiver in the preferred embodiment for providing a sync signal which is compatible with ECL.

High speed sync separation system and method

A frame rate conversion system synchronizes data transfers to and from a VRAM frame buffer which are concurrent, continuous, and asynchronous. The system comprises a frame buffer having a split memory for communicating data to a split output shift register. A frame buffer control supervises writing operations to the split memory at a first frame rate. A display control supervises reading operations from the shift register at a second frame rate which is slower than the first frame rate. The frame buffer control and the display control communicate control signals through double synchronizers. The display control has a counter for counting frames of data which have been read from the VRAM frame buffer. The display control prevents the writing of a frame into the split memory after a particular number of frames has been counted so as to prevent the frame buffer control from writing over and destroying existing data which has not yet been read from the split memory by the display control. Moreover, the display control synchronizes the writing and reading operations by the frame buffer control and the display control, respectively, each time that a frame has been skipped. Furthermore, the frame buffer control causes the VRAM frame buffer to transfer data from the split memory to the shift register when the horizontal blank is deasserted within the incoming analog video signal.

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Ft. Collins, CO, United States of America

Bradly J Foster