International Business Machines Corporation

Globalfoundries Inc.

Bradly George Frey

Cathy May

Guy L Guthrie

Derek E Williams

Michael K Gschwind

Benjamin Herrenschmidt

Anthony J Bybell

Hung Qui Le

William John Starke

Paul Mackerras

Brian William Thompto

Harold Wade Cain, Iii

Jeffrey A Stuecheli

Richard Loise Arndt

Andrew Henry Wottreng

Robert J Blainey

Francis Patrick O'Connell

Harold W Cain

Balaram Sinharoy

Steven Mark Thurber

Lakshminarayana Baba Arimilli

Giles R Frazier

Bernard Charles Drerup

Peter Kenneth Szwed

John David Irish

Christian Zoellin

Michael D Snyder

Jentje Leenstra

James Xenidis

Guerney D H Hunt

Edward John Silha

Debapriya Chatterjee

Gary L Whisenhunt

John Barry Griswell, Jr

George W Rohrbaugh, Iii

Michal Ostrowski

John W Blackledge, Jr

Eric Jason Fluhr

Albert Thomas Williams

Kumar K Gala

Becky Bruce

David D Dukro

Renato John Recio

Maged M Michael

Naresh Nayar

Ramakrishnan Rajamony

Randal Craig Swanberg

Robert H Bell, Jr

Jose Eduardo Moreira

Richard Harold Boivie

Richard James Eickemeyer

Sanjeev Ghai

Susan Elizabeth Eisen

Gregory Francis Pfister

William Eric Hall

Albert James Van Norstrand, Jr

Wen-Tzer Thomas Chen, Jr

Yaoqing Gao

David A Campbell

Miles Robert Dooley

Gary Dean Anderson

Aaron C Brown

Jason Nathaniel Dale

Bechara F Boury

Ronald Xavier Arroyo

John Martin Ludden

Raymond J Pedersen

Charles Brian Hall

Priya Ashok Nagpurkar

Ronald E Valli

James D Reid

A computer system, processor, and/or method for changing the mode of operation of a computer without rebooting includes: a processor having a configuration register, the configuration register having a privilege entry (PRVS) register field for each of one or more privilege levels, each PRVS register field for each privilege level having one or more control aspect entries; and an enforce below (ENFB) register field, each ENFB register field for each privilege level having one or more control aspect entries, the PRVS register field control aspects being equal in number to and corresponding to the ENRB register field control aspects. The PRVS register fields and the ENFB register fields are used to change the processor from a secure mode to a performance mode while running software applications.

Systems and methods for dynamic control of a secure mode of operation in a processor

The present disclosure relates to a process-based virtualization system comprising a data processing unit. The system comprises a computer readable storage media, wherein a first memory component of the computer readable storage media is configured for access by an OS, secure and non-secure applications and the firmware, and wherein a second memory component of the computer readable storage media is configured for access by the firmware and not by the OS and the non-secure application. The data processing unit is configured to operate in a first mode of operation that executes a non-secure application process using the OS, and to operate in a second mode of operation that executes the secure application using the firmware, thereby executing application code using the second memory component.

Process-based virtualization system for executing a secure application process

A processor core processes a translation load instruction including a protection field specifying a desired access protection to be specified in a translation entry for a memory page. Processing the translation load instruction includes calculating an effective address within the memory page and ensuring that a translation entry containing the desired access protection is stored within at least one translation structure of the data processing system.

Translation load instruction with access protection

Operation of a multi-slice processor that includes a plurality of execution slices. Operation of such a multi-slice processor includes: determining, by a hypervisor, that consumption of memory controller resources, by a plurality of processing threads, is above a threshold quantity, wherein respective processing threads of the plurality of processing threads control respective prefetch settings; and responsive to determining that the consumption of the memory controller resources is above the threshold quantity, modifying individual memory controller usage of at least one of the plurality of processing threads such that the consumption of the memory controller resources is reduced below the threshold quantity.

Operation of a multi-slice processor implementing adaptive prefetch control

An apparatus includes a processor and a virtual address transformation unit coupled with the processor. The virtual address transformation unit includes a register. The virtual address transformation unit is configured to receive an indication of a virtual address and read, from the register, a current page size of a plurality of available page sizes. The virtual address transformation unit is also configured to determine a shift amount based, at least in part, on the current page size and perform a bit shift of the virtual address, wherein the virtual address is bit shifted by, at least, the determined shift amount.

Hardware-based pre-page walk virtual address transformation independent of page size utilizing bit shifting based on page size

A processor core among the plurality of processor cores initiates invalidation of translation entries buffered in the plurality of processor cores by executing a translation invalidation instruction in an initiating hardware thread. The processor core also executes, in the initiating hardware thread, a synchronization instruction following the translation invalidation instruction in program order that determines completion of invalidation, at all of the plurality of processor cores, of the translation entries specified by the translation invalidation instruction and draining of any memory referent instructions whose target addresses have been translated by reference to the translation entries. A register is updated to a state based on a result of the determination. The processor core branches execution to re-execute the synchronization instruction based on the state of the register indicating that the translation entries are not invalidated at all of the plurality of processor cores.

Interruptible translation entry invalidation in a multithreaded data processing system

In a data processing system implementing a weak memory model, a lower level cache receives, from a processor core, a plurality of copy-type requests and a plurality of paste-type requests that together indicate a memory move to be performed. The lower level cache also receives, from the processor core, a barrier request that requests enforcement of ordering of memory access requests prior to the barrier request with respect to memory access requests after the barrier request. In response to the barrier request, the lower level cache enforces a barrier indicated by the barrier request with respect to a final paste-type request ending the memory move but not with respect to other copy-type requests and paste-type requests in the memory move.

Efficient enforcement of barriers with respect to memory move sequences

Hardware based isolation for secure execution of virtual machines (VMs). At least one virtual machine is executed via operation of a hypervisor and an ultravisor. A first memory component is configured for access by the hypervisor and the ultravisor, and a second memory component is configured for access by the ultravisor and not by the hypervisor. A first mode of operation is operated, such that the virtual machine is executed using the hypervisor, wherein the first memory component is accessible to the virtual machine and the second memory component is not accessible to the virtual machine. A second mode of operation is operated, such that the virtual machine is executed using the ultravisor, wherein the first memory component and the second memory component are accessible to the virtual machine, thereby executing application code and operating system code using the second memory component without code changes.

Hardware based isolation for secure execution of virtual machines

Hardware-based pre-page walk virtual address transformation where the virtual address is shifted by current page size and a minimum page size

A processor core has a store-through upper level cache and a store-in lower level cache. In response to execution of a memory move instruction sequence including a plurality of copy-type instruction and a plurality of paste-type instructions, the processor core transmits a corresponding plurality of copy-type and paste-type requests to the lower level cache, where each copy-type request specifies a source real address and each paste-type request specifies a destination real address. In response to receipt of each copy-type request, the lower level cache copies a respective one of a plurality of data granules from a respective storage location specified by the source real address of that copy-type request into a non-architected buffer. In response to receipt of each paste-type request, the lower level cache writes a respective one of the plurality of data granules from the non-architected buffer to a respective storage location specified by the destination real address of that paste-type request.

Memory move instruction sequence including a stream of copy-type and paste-type instructions

In a multithreaded data processing system including a plurality of processor cores, storage-modifying requests, including a translation invalidation request of an initiating hardware thread, are received in a shared queue. The translation invalidation request is broadcast so that it is received and processed by the plurality of processor cores. In response to confirmation of the broadcast, the address translated by the translation entry is stored in a queue. Once the address is stored, the initiating processor core resumes dispatch of instructions within the initiating hardware thread. In response to a request from one of the plurality of processor cores, an effective address translated by a translation entry being invalidated is accessed in the queue. A synchronization request for the address is broadcast to ensure completion of processing of any translation invalidation request for the address.

Translation entry invalidation in a multithreaded data processing system

In a multithreaded data processing system including a plurality of processor cores, storage-modifying requests, including a translation invalidation request of an initiating hardware thread, are received in a shared queue. The translation invalidation request is broadcast so that it is received and processed by the plurality of processor cores. In response to confirmation of the broadcast, the address translated by the translation entry is stored in a queue. Once the address is stored, the initiating processor core resumes dispatch of instructions within the initiating hardware thread. In response to a request from one of the plurality of processor cores, an effective address translated by a translation entry being invalidated is accessed in the queue. A synchronization request for the address is broadcast to ensure completion of processing of any translation invalidation request for the address. Subsequent memory referent instructions can be ordered with respect to the broadcast synchronization request by a synchronization instruction.

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Austin, TX, United States of America

Bradly George Frey