International Business Machines Corporation

Bradley Paul Jones

Richard Paul Volant

Christian Lavoie

Viraj Yashawant Sardesai

Michael F Lofaro

Robert J Purtell

Fen Fen Jamin

Kenneth M Davis

Sameer T Shikalgar

Yutong Wu

Michael J Toner

Yun Yu Wang

Keith Kwong Hon Wong

Yun-Yu Wang

Kwong Hon Wong

Hiroyuki Akatsu

Sarah Huffsmith Knickerbocker

Anthony Gene Domenicucci

Francis R Krug, Jr

Russell Herbert Arndt

Anthony C Speranza

Ralph R Comulada

George F Ouimet, Jr

A method of protecting a mold having at least one substantially planar surface provided with a plurality of mold cavities includes inserting a plurality of mandrels into respective ones of the plurality of mold cavities, depositing a layer of mold protection material onto the at least one substantially planar surface and the plurality of mandrels, and removing the plurality of mandrels from the mold substrate.

Protecting a mold having a substantially planar surface provided with a plurality of mold cavities

Methods, systems, and computer program products for managing movement of work-in-process materials between processing units in an automated manufacturing environment are provided. A system includes a host system in communication with a work-in-process (WIP) material lot. The system also includes an application executing on the host. The application implements a method that includes tracking a position of the WIP material lot, receiving a list of the processing units designated to be inoperative during a down time, and receiving a start time and a duration of the down time. The method also includes determining a maximum dwell time for each of the designated processing units and scheduling movement of the WIP material lot during an interim between a current time and the start time of the down time based on current position of the work-in-process material lot, the current time, the start time and duration of the down time, and the maximum dwell time.

Methods, systems, and computer program products for managing movement of work-in-process materials in an automated manufacturing environment

The present invention provides a method for enhancing uni-directional diffusion of a metal during silicidation by using a metal-containing silicon alloy in conjunction with a first anneal in which two distinct thermal cycles are performed. The first thermal cycle of the first anneal is performed at a temperature that is capable of enhancing the uni-directional diffusion of metal, e.g., Co and/or Ni, into a Si-containing layer. The first thermal cycle causes an amorphous metal-containing silicide to form. The second thermal cycle is performed at a temperature that converts the amorphous metal-containing silicide into a crystallized metal rich silicide that is substantially non-etchable as compared to the metal-containing silicon alloy layer or a pure metal-containing layer. Following the first anneal, a selective etch is performed to remove any unreacted metal-containing alloy layer from the structure. A second anneal is performed to convert the metal rich silicide phase formed by the two thermal cycles of the first anneal into a metal silicide phase that is in its lowest resistance phase. A metal silicide is provided whose thickness is self-limiting.

Method for enhanced uni-directional diffusion of metal and subsequent silicide formation

A method for forming a metal silicide contact for a semiconductor device includes forming a refractory metal layer over a substrate, including active and non-active area of said substrate, and forming a cap layer over the refractory metal layer. A counter tensile layer is formed over the cap layer, wherein the counter tensile layer is selected from a material such that an opposing directional stress is created between the counter tensile layer and the cap layer, with respect to a directional stress created between the refractory metal layer and the cap layer.

Method for controlling voiding and bridging in silicide formation

A method for planarizing a dielectric layer on a semiconductor wafer is provided. In one aspect, the wafer is coated with a resist and the resist selectively removed forming an uncoated peripheral portion of the wafer. The partially coated wafer is then exposed to an etchant such as RIE to etch the dielectric material not covered by the resist and forming a profiled dielectric layer having a thinner peripheral dielectric portion and a remaining thicker original dielectric central portion. The profiled wafer is then planarized using CMP. The dielectric layer is typically SiO , PSG, BSP, or BPSG. In another method and apparatus of the invention, a dielectric coated wafer is secured to a rotating turntable and a liquid etchant sprayed at the periphery of the wafer from a distribution conduit to etch and remove dielectric from a circumferential edge of the wafer forming a profiled dielectric layer as above which is then planarized by CMP. In another aspect of the invention, a CMP polished semiconductor wafer having an edge bead is planarized by polishing only the edge bead of the dielectric layer using a special polishing tool or a CMP apparatus to remove the edge bead from the dielectric layer. Planarized semiconductor wafers made using the method and apparatus of the invention are also provided.

Semiconductor wafer edge bead removal method and tool

A system for chemical-mechanical polishing is described which includes a wafer backing film having concentric first and second portions. The portions of the wafer backing film are of different materials. The second portion of the wafer backing film has an annular shape and surrounds the first portion; a backing shim is used to adjust the first portion and second portion with respect to each other in a vertical direction. The first and second portions of the wafer backing film and the backing shim are mounted on an adhesive assembly film, thereby forming an assembly for mounting on a wafer carrier. The second portion of the wafer backing film is less compressible than the first portion, and is adjusted in the vertical direction so that the outer edge of the wafer is substantially sealed when backside air is applied to the wafer during a film removal process.

Chemical-mechanical polishing system having a bi-material wafer backing film assembly

A system for chemical-mechanical polishing is described which includes a wafer backing film having concentric first and second portions, and a wafer carrier having corresponding first and second portions for mounting the portions of the wafer backing film thereon. The portions of the wafer backing film are of different materials. The second portion of the wafer backing film has an annular shape and surrounds the first portion; the second portion of the wafer carrier is adjustable with respect to the first portion of the wafer carrier in a vertical direction. The second portion of the wafer backing film is less compressible than the first portion, and is adjusted in the vertical direction so that the outer edge of the wafer is substantially sealed when backside air is applied to the wafer during a film removal process.

Chemical-mechanical polishing system having a bi-material wafer backing film and two-piece wafer carrier

A method for planarizing a dielectric layer on a semiconductor wafer is provided. In one aspect, the wafer is coated with a resist and the resist selectively removed forming an uncoated peripheral portion of the wafer. The partially coated wafer is then exposed to an etchant such as RIE to etch the dielectric material not covered by the resist and forming a profiled dielectric layer having a thinner peripheral dielectric portion and a remaining thicker original dielectric central portion. The profiled wafer is then planarized using CMP. The dielectric layer is typically SiO.sub.2, PSG, BSP, or BPSG. In another method and apparatus of the invention, a dielectric coated wafer is secured to a rotating turntable and a liquid etchant sprayed at the periphery of the wafer from a distribution conduit to etch and remove dielectric from a circumferential edge of the wafer forming a profiled dielectric layer as above which is then planarized by CMP. In another aspect of the invention, a CMP polished semiconductor wafer having an edge bead is planarized by polishing only the edge bead of the dielectric layer using a special polishing tool or a CMP apparatus to remove the edge bead from the dielectric layer. Planarized semiconductor wafers made using the method and apparatus of the invention are also provided.

An integrated circuit (IC) conductor and the process of making the conductor. The conductor may be a monofilament conductor, a clad conductor or a coaxial conductor. A trench is formed in a dielectric layer. An outer material layer is deposited on the dielectric layer and in the trench, thick enough that the outer material layer merges together in a seam over the trench forming a void under the seam. The outer material layer is dielectric for the monofilament conductor, a cladding material for the clad conductor and conducting material for the coaxial conductor. The void is filled with a conductor for a monofilament or clad conductors. An inner dielectric liner layer is formed on the walls of the void and a core conductor is formed on the liner layer for the coaxial conductor.

Conductors for microelectronic circuits and method of manufacture

The present invention discloses a method of doping and preventing silicide formation in selective areas of a polysilicon gate in MOS, PMOS, NMOS or CMOS manufacturing technologies. The process includes the steps of: depositing a non-conformal dopant containing layer on the top surface of the body and the top surface of the polysilicon gate; removing a portion of the non-conformal dopant containing layer to expose the top surface of the polysilicon gate; and heating to diffuse dopant from the dopant containing layer. Silicidation is then provided by depositing a metal layer and annealing the metal layer. As a first alternative method, the heating and removing step may be reversed. As a second alternative method, after removal of the non-conformal layer, a metal layer can be deposited followed by a combination anneal of the metal layer and non-conformal dopant containing layer.

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Wappingers Falls, NY, United States of America

Bradley Paul Jones