Globalfoundries Inc.

Globalfoundries U.S. Inc.

Bradley Morgenfeld

Rui Chen

Cung D Tran

Ravi Prakash Srivastava

Xintuo Dai

Sanggil Bae

Dongyue Yang

Minghao Tang

Md Motasim Bellah

Pavan Kumar Chinthamanipeta Sripadarao

Huaxiang Li

Christian J Ayala

Kripa Nidhan Chauhan

Julien Frougier

Haiting Wang

Daniel J Jaeger

Michael Vincent Aquilino

Man Gu

Ali Razavieh

Yuping Ren

Wang Zheng

Zheng G Chen

Ming Hao Tang

Kavya Sree Duggimpudi

One illustrative transistor device disclosed herein includes a nanowire matrix comprising a plurality of nanowire structures that are arranged in at least one substantially horizontally oriented row and at least two substantially vertically oriented columns, the at least two substantially vertically oriented columns being laterally spaced apart from one another in a gate width direction of the transistor device, each of the plurality of nanowire structures comprising an outer perimeter. This illustrative embodiment of the transistor device further includes a gate structure that is positioned around the outer perimeter of all of the nanowire structures in the matrix, and a gate cap positioned above the gate structure.

Transistor comprising a matrix of nanowires and methods of making such a transistor

A semiconductor device is provided, which includes an array of active regions, gate stacks and substantially uniform epitaxial structures. The gate stacks of the array include a first gate stack and a second gate stack over an active region. An active pillar between the first gate stack and the second gate stack, and the active pillar separating two substantially uniform epitaxial structures. A contact structure over the active pillar, positioned equidistant from the first gate stack and the second gate stack.

Epitaxial structures of a semiconductor device having a wide gate pitch

In an exemplary method, a first layer is formed on a substrate. First overlay marks are formed in a first zone of the first layer. A non-transparent layer is formed on top of the first layer. At least a portion of the non-transparent layer is removed from an area above the first zone of the first layer. This provides optical access to the first overlay marks. A second layer is formed on top of the non-transparent layer. Second overlay marks are formed in a second zone of the second layer. Position information is obtained from each of the first overlay marks and the second overlay marks.

Structure and method to improve overlay performance in semiconductor devices

This disclosure relates to a structure for aligning layers of an integrated circuit (IC) structure that may include a first dielectric layer positioned above a semiconductor substrate having one or more active devices, a trench stop layer positioned above the first dielectric layer, a second dielectric layer positioned above the trench stop layer, and a plurality of metal-filled marking trenches extending vertically through the second dielectric layer and the trench stop layer and at least partially into the first dielectric layer. The metal-filled trenches are electrically isolated from any active devices contained in the IC.

Mark structure for aligning layers of integrated circuit structure and methods of forming same

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Greenfield Center, NY, United States of America

Bradley Morgenfeld