Microsoft Technology Licensing, LLC

Bradley Michael Waters

Bradford Michael Beckmann

Neel K Jain

Amol Dilip Dixit

Niklas Gustafsson

Jee Fung Pang

Mahlon David Fields

Danyu Zhu

Mahlon David Fields, Jr

A memory allocation system is provided and includes nodes, one or more memories, and an allocation interface. Each of the nodes includes a respective set of processors. The one or more memories include memory elements for storing threads. The memory elements refer to respective portions of the one or more memories and are accessible to at least one of the nodes. The allocation interface is configured to allocate the memory elements to lockless list structures. Each of the lockless list structures is allocated to a respective set of the memory elements. The lockless list structures are partitioned for the processors. The allocation interface is configured to receive requests from the processors for the memory elements and adjust allocation of the memory elements between the lockless list structures according to a balancing metric.

Allocation systems and method for partitioning lockless list structures

Systems and techniques of the management of the allocation of a plurality of memory elements stored within a plurality of lockless list structures are presented. These lockless list structures (such as Slists) may be made accessible within an operating system environment of a multicore processor&#x2014;and may be partitioned within the system. Memory elements may also be partitioned among these lockless list structures. When a core processor (or other processing element) makes a request for allocating a memory element to itself, the system and/or method may search among the lockless list structures for an available memory element. When a suitable and/or available memory element is found, the system may allocate the available memory element to requesting core processor. Dynamically balancing of memory elements may occur according to a suitable balancing metric, such as maintain substantial numerical equality of memory elements or avoid over-allocation of resources.

Systems and methods for S-list partitioning

Various embodiments provide an ability to schedule latency-sensitive tasks based, at least in part, upon one or more processor cores usage metrics. Some embodiments gather information associated with whether one or more processor cores are in a heavily loaded state. Alternately or additionally, some embodiments gather information identifying latency-sensitive tasks. Task(s) can be (re)assigned to different processor core(s) for execution when it has been determined that an originally assigned processor core has exceeded a usage threshold.

Latency sensitive software interrupt and thread scheduling

Protection entries and techniques for providing fine granularity computer memory protection are described herein. A method of protecting a computer memory may include separating or parsing the computer memory, containing data or code, into blocks and creating protection entries for each block. The protection entries optionally include a reference field for identifying a block of memory, and a protection field for specifying one or more levels of access to the identified block of memory. The protection entries may then be used to pass messages between various system entities, the messages specifying one or more levels of access to the one or more blocks of memory or code.

Fine granularity hierarchiacal memory protection

Software assists a processor subsystem in making cache replacement decisions by providing an intermediary with information regarding how instructions and/or data of a working set are expected to be used and accessed by the software. The intermediary uses this information along with its knowledge of system requirements, policy and the cache configuration to determine cache usage and management hints for the working sets. The cache usage and management hints are passed by the intermediary to the processor subsystem.

Processor cache management with software input via an intermediary

A processor cache is indexed by a group of distinct page colors. The use of this cache by different working sets is controlled using page coloring. Translations of virtual addresses of the instructions and/or data of a working set are constrained to physical addresses the page colors of which are in a subgroup of the group of distinct page colors.

Managing working set use of a cache via page coloring

Performing atomic operations on data entities having an arbitrary size is disclosed. Version data is associated with a data entity. The version data is saved to a first attribute. The data entity is then accessed. The saved version data is compared to the current version data. If the two are equal, the data entity is valid.

Atomic operations on data structures

An event tracing program generally receives performance data about an event occurring on the computer system from a data producer program. The event tracing program responds by recording the event performance data in one of a set of a log buffers. When a log buffer becomes full, the event tracing program places the log buffer on a buffer flush list. The filled buffer is then written out to a more permanent storage medium, such as a disk. From time to time, the event tracing program may also transfer a buffer to the flush list prior to becoming full after a time-out period. To prevent a buffer from being flushed while event performance data is being recorded in the buffer, a reference count is incremented prior to the record operation to signify that the buffer is currently being modified. For high performance on multiprocessor systems, the buffers are allocated per processor to minimize data sharing among processors.

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Woodinville, WA, United States of America

Bradley Michael Waters