Xilinx, Inc.

Sima Technologies, Inc.

Bradley L Taylor

Ting Lu

Sagheer Ahmad

Shay Ping Seng

Hy V Nguyen

Hassan K Bazargan

William Edward Allaire

Shashank Bhonge

Roger Brent Milne

L James Hwang

Patrick J Crotty

Ygal Arbel

Arvind Sundararajan

Sandeep Dutta

Ahmad R Ansari

Jonathan B Ballagh

Nabeel Shirazi

Jeffrey Stroomer

Chi Bun Chan

Nishit Harshad Shah

Srivathsa Dhruvanarayan

Kavitha Prasad

Robert L Pelt

Reed Kotler

Tomai Knopp

Kam-Wing Li

Alexander R Vogenthaler

Yogesh Laxmikant Chobe

Moenes Zaher Iskarous

Giulio Corradi

Spenser Don Gilliland

Alexander Carreira

Sedny S J Attia

A system-on-chip (SoC) integrated circuit product includes a machine learning accelerator (MLA). It also includes other processor cores, such as general purpose processors and application-specific processors. It also includes a network-on-chip for communication between the different modules. The SoC implements a heterogeneous compute environment because the processor cores are customized for different purposes and typically will use different instruction sets. Applications may use some or all of the functionalities offered by the processor cores, and the processor cores may be programmed into different pipelines to perform different tasks.

Heterogeneous computing on a system-on-chip, including machine learning inference

A method for operating a programmable IC is disclosed. A set of circuits specified by a set of configuration data is operated in a set of programmable resources. In response to one of a set of status signals indicating an error, a value indicative of an error is stored in a respective one of a plurality of error status registers. The values stored in the plurality of error status registers are provided to an error handling circuit included in the set of circuits specified by the set of configuration data and operated in the programmable resources. At least one error handling process is performed by the error handling circuit as a function of values stored in the plurality of error status registers.

User-configurable error handling

An integrated circuit can include a processor system configured to execute program code. The processor system can be hard-wired and include a processor hardware resource. The IC also can include a programmable circuitry configurable to implement different physical circuits. The programmable circuitry can be coupled to the processor system. The programmable circuitry can be configurable to share usage of the processor hardware resource of the processor system. The processor system further can control aspects of the programmable circuitry such as power on and/or off and also configuration of the programmable circuitry to implement one or more different physical circuits therein.

Integrated circuit with programmable circuitry and an embedded processor system

A system on a chip (SoC) for providing safety hardware fault tolerance and/or safety software fault tolerance includes a first safety sub-system having a first safety channel; a second safety sub-system having a second safety channel; and a third sub-system. The first safety sub-system is independent of the second safety sub-system to allow the second safety sub-system to communicate through the second safety channel when the first safety sub-system or the third subsystem fails, and further to allow the first safety sub-system to communicate through the first safety channel when the second safety sub-system or the third subsystem fails.

Safety hardware and/or software fault tolerance using redundant channels

Method and apparatus for monitoring system operations in an integrated circuit. A method includes receiving a first power supply voltage from a first processing domain, comparing the first power supply voltage to a first reference voltage, receiving the second power supply voltage from the second processing domain, comparing the second power supply voltage to a second reference voltage, determining that the first power supply voltage exceeds the first reference voltage or that the second power supply voltage exceeds the second reference voltage, and transmitting one or more alarms corresponding to one or more of the first power supply voltage and the second power supply voltage in response to determining that the first power supply voltage exceeds the first reference voltage or that the second power supply voltage exceeds the second reference voltage. An integrated circuit and system monitor are also provided.

Cross-coupled voltage and temperature monitoring in programmable integrated circuits

A method of extending a processor system within an integrated circuit (IC) can include executing program code within the processor system implemented within the IC, wherein the IC includes a programmable fabric. The processor system further can be coupled to the programmable fabric. A process can be performed using a process-specific circuit implemented within the programmable fabric in lieu of using the processor system. A result of the process from the process-specific circuit can be made available to the processor system.

Extending a processor system within an integrated circuit and offloading processes to process-specific circuits

A programmable IC is disclosed that includes a programmable logic sub-system, a processing sub-system, and a safety sub-system. The programmable logic sub-system includes programmable logic circuits configured to form a hardware portion of a user design. The processing sub-system includes processing circuits configured to execute a software portion of a user design. The safety sub-system is configured to perform a safety functions that detect and/or mitigate errors in circuits of the programmable IC. The safety sub-system includes hard-wired circuits configured to perform hardware-based safety functions for a first subset of circuits of the programmable IC. The safety sub-system also includes a processing circuit configured to execute software-based safety functions for a second subset of circuits of the programmable IC.

Programmable IC with safety sub-system

A circuit for providing isolation in an integrated circuit is described. The circuit comprises a first circuit block having circuits associated with a first security level; a second circuit block having circuits associated with a second security level; and a third circuit block having programmable resources, the third circuit block providing isolation between the first circuit block and the second circuit block and being programmable to enable connections between the first circuit block and the second circuit block.

Circuits for and methods of providing isolation in an integrated circuit

An integrated circuit can include a processor system configured to execute program code, wherein the processor system is hard-wired. The IC also can include programmable circuitry configurable to implement different physical circuits. The programmable circuitry can be coupled to the processor system and can be configured to implement a power off procedure under the control of the processor system.

Power management within an integrated circuit

A method of debugging an integrated circuit (IC) can include receiving, within a debugging system implemented within the IC, a debug command from a system external to the IC and, responsive to the debug command, initiating a debug function specified by the debug command for a processor system embedded on the IC. An IC also is provided that can include a programmable circuitry (e.g., a programmable fabric) coupled via an interface to processor system embedded in the IC. A debugging system can be implemented within the programmable fabric to communicate with the processor system via the interface.

Debugging an integrated circuit with an embedded processor

A method of debugging within an integrated circuit (IC) that includes an embedded processor can include detecting an event within a circuit of the IC that is external to the processor and, responsive to detecting the event, initiating a debug function within the processor. Similarly, responsive to detecting an event within the processor, a debug function within a circuit block of the IC that is external to the processor can be initiated. Trace data generated within the processor and trace data generated within the programmable fabric further can be merged to generate combined trace data.

Integrated debugging within an integrated circuit having an embedded processor

A device having programmable logic for implementing arithmetic functions is disclosed. The device comprises an input port coupled to receive a configuration bitstream; a plurality of configurable arithmetic blocks, each configurable arithmetic block comprising configurable circuits for implementing arithmetic functions according to bits of the configuration bitstream; a plurality of input registers coupled to receive multi-bit input words to be processed by the plurality of configurable arithmetic blocks; and an output register enabled to generate an output word. A method of implementing an arithmetic function in a device having programmable logic is also disclosed.

Device having programmable logic for implementing arithmetic functions

An embodiment of a system for implementing parallel usage of a plurality of non-volatile input/output (I/O) devices can include an interface configured to receive, from a source, a source request and a first memory coupled to the interface. The first memory can be configured to store a data unit specified by the source request. The system can include an I/O device controller coupled to the interface. The I/O device controller can be configured to correlate the source request with a plurality of I/O device requests and initiate sending of the plurality of I/O device requests to the plurality of non-volatile I/O devices in parallel. The system also can include a decoder coupled to the first memory and the I/O device controller. The decoder can be configured to receive data from the plurality of non-volatile I/O devices in parallel.

Data operations across parallel non-volatile input/output devices

A configurable arithmetic block in a device having programmable logic for implementing arithmetic functions is disclosed. The configurable arithmetic block comprises a plurality of input registers coupled to receive multiple bit words; an arithmetic function circuit coupled to receive the multiple bit words; an output selection circuit coupled to receive the output of the plurality of input registers and an output of the arithmetic function circuit; and a plurality of output registers coupled the output selection circuit. A method of implementing arithmetic functions in a device having programmable logic is also disclosed.

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Santa Cruz, CA, United States of America

Bradley L Taylor