Intel Corporation

Dell Products Inc.

Applied Micro Circuits Corporation

Jato Technologies, Inc.

Bradley John Booth

Jimmy Doyle Pike

Shawn Joel Dube

Robert Wayne Hormuth

Robert L Winter

Geng Lin

Mark T Feuerstraeter

Rabah S Hamdi

Ilango S Ganga

Luke L Chang

Robert O Sharp

Harlan Titus Beverly

Henning Lysdal

Quang T Le

Paul J Weldon

Percy W Wong

Nestor A Fesas, Jr

William Kass

Mark Feuerstraeter

An input/output (I/O) device includes a management controller interface, a plurality of network switching interfaces, a storage interface, a component controller interface, and a plurality of multifunction modules. The multifunction modules further include a processing node interface, a first endpoint coupled to the management controller interface, a second endpoint coupled to one of the plurality of network switching interfaces, a third endpoint coupled to a remote direct memory access (RDMA) block, a fourth endpoint coupled to the storage interface, and a fifth endpoint coupled to the component controller interface.

System and method for providing input/output functionality by an I/O complex switch

A processing node of a server rack includes a processor to generate processing node management requests and to process responses to the node management requests, and a communication module to receive the processing node management requests, to transmit over a communication link to a management controller of the server rack external to the processing node a processing node management request, to receive over the communication link from the management controller processing node management information, and to transmit the processing node management information to the processor.

System and method for providing a processing node with input/output functionality provided by an I/O complex switch

A power sourcing equipment (PSE) device including a power over Ethernet (PoE) interface. A processor is coupled to the PoE interface. A memory is coupled to the processor and includes instruction that, when executed by the processor, cause the processor to perform a number of functions. The processor may supply power at a first power level to a PD that is coupled to the PoE interface. The processor may then determine an actual power consumption of the PD. The processor may then send a first Link Layer Discovery Protocol (LLDP) packet to the PD over the PoE interface that includes first proposed power level information that is based on the actual power consumption of the PD. Then processor may then supply power to the PD at a second power level that is different from the first power level.

Dynamic power supply system

A system includes first and second processing nodes and a network switch coupled to the first and second processing nodes via respective first and second interfaces. The network switch includes a management controller coupled to the interfaces to provide management functions to the processing nodes, first and second network interfaces coupled respectively to the first and second interfaces to provide network access for the processing nodes, a message passing interface between the first processing node and the second processing node, a storage interface coupled to the first and second interfaces to provide a storage capacity to the processing nodes, and a remote component controller coupled to the interfaces.

System and method for providing a processing node with input/output functionality by an I/O complex switch

Power over ethernet (POE) dynamic power supply system

A network interface controller includes a plurality of host interfaces configured to communicate with a plurality of processing nodes, a plurality of network interfaces configured to provide network communication for the processing nodes to a network, and a shared resource configured to provide link based services and stateless offload services for the processing nodes when communicating with the network.

System and method for providing network access for a processing node

Advanced PoE power control

A remote component controller of a server rack includes a real time clock information unit to maintain real clock time and to respond to requests for real time clock information, and a communication module to receive over a communication link a request from a processing node of the server rack for real time clock information, to forward the request to the real time clock information unit, to receive from the real time clock information unit a response to the request, and to transmit the response to the request to the processing node over the communication link.

System and method for providing input/output functionality to a processing node

In a communication device using a plurality of signal enhancement mechanisms, a system and method are provided for managing signal processing power consumption. A receiver accepts a communications signal and analyzes signal integrity. In response to analyzing the signal integrity, a signal enhancement mechanism is changed, and device power consumption is modified in response to changing the signal enhancement mechanism. In one aspect, the receiver changes a receiver signal enhancement mechanism, and modifies its power consumption. For example, one or more of the following receiver signal enhancement mechanisms may be selected: forward error correction (FEC), equalization, dc voltage level, and physical coding sublayer (PCS).

System and method for closed-loop optical network power backoff

A system and method are provided for securing links at the physical (PHY) layer in an IEEE 802.3 Ethernet communication system. A local device (LD) receives an electrical waveform representing link partner security information from a network-connected link partner (LP) via unformatted message pages. The LD accesses predetermined LP reference information stored in a tangible memory medium. The LD compares the received LP security information to the LP reference information. In response to the LD matching the received LP security information to the LP reference information, a secure link to the LP is verified. Likewise, the LD may send electrical waveforms representing security information to the LP via the unformatted message pages. In response to the LP matching the LD security information to the LD reference information, a secure link to the LD is verified.

Ethernet PHY level security

A system and method are provided for accelerating forward error correction (FEC) synchronization in a communicating receiver. On the transmitter side, the method accepts an energy waveform representing a packet of data symbols, encodes the packet, and creates an FEC block. Prior to transmitting the FEC block, an electromagnetic waveform is transmitted representing an FEC flag character. Then, an electromagnetic waveform representing the FEC block is transmitted a predetermined first period of time after the transmission of the FEC flag character. For example, the first time period may be immediately following the FEC flag character transmission or a predetermined number of idle characters following the transmission of the FEC flag character.

System and method for accelerated forward error correction (FEC) synchronization

Disclosed are a system, method and device for negotiating a data transmission mode over an attachment unit interface (DDI). A data transceiver circuit may be coupled to one or more data lanes of the DDI. A negotiation section may receive a link pulse signal on at least one data lane in the DDI during a negotiation period and selectively configure the data transceiver to transmit and receive data on one or more data lanes according to a data transmission mode based upon the received link pulse signal.

System, method and device for autonegotiation

An interface and related methods for rate pacing in an Ethernet architecture are described herein. In an embodiment, an effective data rate of communication channel with a remote network device is reduced based, at least in part, on an identified processing capability of the remote network device. In one embodiment, to reduce the effective data rate, one or more idle control elements are inserted between at least two frames of substantive content based, at least in part, on the processing capability of the remote network device. Other embodiments are also disclosed.

Interface and related methods for rate pacing in an ethernet architecture

Described are a device and system to transmit data to or receive data from one or more data lane interfaces. Each data lane interface may be capable of transmitting a serial data signal to or receiving a serial data signal from a data lane in a device-to-device interconnection. An effective data rate may be varied based, at least in part, upon a number of the data lane interfaces actively transmitting a serial data signal to or receiving a serial data signal from the device-to-device interconnection.

Growing community of inventors

Austin, TX, United States of America

Bradley John Booth