Atmel Corporation

Aeroflex Utmc Microelectronic Systems, Inc.

Bradley J Larsen

Todd A Randazzo

Donald A Erickson

Geoffrey S Gongwer

David B Kerwin

Amit S Kelkar

Nicolas Degors

Kurt Schertenleib

Timothy M Barry

A radiation-hardened STI process includes implanting a partially formed wafer with a fairly large dose (10to 10ions/cm) of a large atom group III element, such as B, Al, Ga or In at an energy between about 30 and 500 keV. The implant is followed by an implant of a large group V element, such as P, As, Sb, or Bi using similar doses and energies to the group III element. The group V element compensates the group III element. The combination of the two large atoms decreases the diffusivity of small atoms, such as B, in the implanted areas. Furthermore, the combination of the group III and group V elements in roughly equal proportions creates recombination sites and electron traps in the field oxide, resulting in a radiation hardened semiconductor device.

Radiation hardening method for shallow trench isolation in CMOS

A method for fabricating a shallow trench isolation structure is described, in which a bottom pad oxide layer, a middle silicon nitride layer, a middle oxide layer and a top silicon nitride layer are sequentially formed on a silicon substrate. Photolithographic masking and anisotropic etching are then conducted to form a trench in the substrate. An oxide material is then deposited on top of the top silicon nitride layer, filling up the trenches at the same time. A chemical mechanical polishing step is then employed to remove the oxide material by using the top silicon nitride layer as a barrier layer. The top silicon nitride layer is then removed, followed by an isotropic etch of the oxide layer below. With the middle nitride layer acting as a natural etch stop, the oxide material is sculpted to a desirable shape. The middle nitride layer and the pad oxide layer are subsequently removed to complete the fabrication of a shallow trench isolation structure.

Method of forming shallow trench isolation structure in a semiconductor device

A contact of large dimensions having a stringer strongly adhered to a contact hole's sidewalls. The contact hole is made to have a patterned perimeter having grooves protruding outward. The grooves have a size equal to a minimum contact dimension in at least one direction so as to ensure good step coverage into the groove areas. The grooves serve to anchor the stringer to the contact hole sidewalls by increasing the sidewall's surface area which increases adhesion, distributing stress from the stringer to the groove areas, and providing grooves with good step coverage.

Integrated circuit contacts with secured stringers

An apparatus providing electrostatic discharge (ESD) protection in an input/output transistor. Disposed near the gate and the surface of the substrate is a lightly doped region. A sidewall oxide layer is selectively etched to extend laterally from a gate a significant amount. The sidewall oxide layer is also etched on an opposite side of the gate and may laterally extend an appreciable amount in that direction. A heavily doped source and drain are implanted in the substrate at areas of the surface exposed by etching, the drain separated from the gate by the significant extent of sidewall oxide. Near the surface of the substrate, the drain is separated from the gate by a similar extent of the lightly doped region, which provides a resistance in series between the drain and gate for ESD protection. The source may also be separated from the gate by a lightly doped region of appreciable extent, which acts as a series resistance between the source and the gate to mitigate ESD. The extent of the sidewall oxide, and thus the lightly doped regions separating the gate from the drain and source, can be tailored to optimize ESD protection and performance characteristics for a given application by defocusing snapback conduction.

Input/output transistors with optimized ESD protection

An EEPROM transistor fabricated with a single polysilicon layer. An MOS transistor is fabricated with a subsurface electrode region defined by a stripe in a first direction. A layer of thin oxide is arranged in a second stripe, perpendicular to the first stripe and a polysilicon layer, arranged in a third stripe is disposed over the second stripe of thin oxide. An adjoining parallel plate capacitor is formed by a subsurface region of the same conductivity type as the subsurface electrodes in the first stripe. An insulative second plate of thin oxide is joined to the second stripe and a third plate of the capacitor is formed by a polysilicon plate over the oxide plate. Vertical metallization stripes in the first direction may contact with some components, while parallel metal stripes in a second layer in a perpendicular direction may contact with the remaining members. The stripe geometry allows lateral and vertical four-way symmetry for implementation of a large number of memory storage cells on a chip or wafer.

Single layer polysilicon EEPROM having uniform thickness gate

A method for making submicron dielectric windows for electron tunneling between a floating gate and substrate in a semiconductor EEPROM device. A mask edge overlying an oxide layer on a substrate is undercut a small distance, the area surrounding that small distance is built up with oxide, then a thin layer of oxide is formed in the undercut distance to serve as a tunneling window.

Method for forming thin tunneling windows in EEPROMs

An apparatus and method for integrating a submicron CMOS device and a non-volatile memory, wherein a thermal oxide layer is formed over a semiconductor substrate and a two layered polysilicon non-volatile memory device formed thereon. A portion of the thermal oxide is removed by etching, a thin gate oxide and a third layer of polysilicon having a submicron depth is deposited onto the etched region. The layer of polysilicon is used as the gate for the submicron CMOS device. In so doing a submicron CMOS device may be formed without subjecting the device to the significant re-oxidation required in formation processes for dual poly non-volatile memory devices such as EPROMs and EEPROMs, and separate device optimization is achieved.

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Woodland Park, CO, United States of America

Bradley J Larsen