Honeywell International Inc.

Bradley J Larsen

Paul S Fechner

Todd A Randazzo

Michael S Liu

Keith W Golke

Thomas R Keyser

Cheisan J Yue

David Owen Erstad

James E Riekels

Gregor D Dougal

Gary R Gardner

David J Swanson

Thomas B Lucking

A method of increasing the radiation hardness of a semiconductor device using a modified high density plasma oxide (MHDPDX) film is described. In the method a high density plasma (HDP) process is used to deposit the MHDPDX film. During the HDP process, the silicon source gas to oxygen source gas ratio is chosen so as to deposit an excess silicon content within the MHDPDX film. The MHDPDX film is then annealed to cause the excess silicon to migrate and amalgamate, creating silicon nanoclusters having an average size of about 3-5 nm. The rad-hard properties of conventional BPSG films and various MHDPDX films are then compared.

Method of fabricating total dose hard and thermal neutron hard integrated circuits

Neutron detection cells and corresponding methods of detecting charged particles that make efficient use of silicon area are set forth. Three types of circuit cells/arrays are described: state latching circuits, glitch generating cells, and charge loss circuits. An array of these cells, used in conjunction with a neutron conversion film, increases the area that is sensitive to a strike by a charged particle over that of an array of SRAM cells. The result is a neutron detection cell that uses less power, costs less, and is more suitable for mass production.

Neutron detector cell efficiency

A method of manufacturing a neutron detector comprises forming a first wafer by at least forming an oxide layer on a substrate, forming an active semiconductor layer on the oxide layer, and forming an interconnect layer on the active semiconductor layer, forming at least one electrically conductive pathway extending from the interconnect layer through the active semiconductor layer and the oxide layer, forming a circuit transfer bond between the interconnect layer and a second wafer, removing the substrate of the first wafer after forming the circuit transfer bond, depositing a bond pad on the oxide layer after removing the substrate of the first wafer, wherein the bond pad is electrically connected to the electrically conductive pathway, depositing a barrier layer on the oxide layer after removing the substrate of the first wafer, and depositing a neutron conversion layer on the barrier layer after depositing the barrier layer.

Neutron detector with wafer-to-wafer bonding

A process flow for fabricating shallow trench isolation (STI) devices with direct body tie contacts is provided. The process flow follows steps similar to standard STI fabrication methods except that in one of the etching steps, body tie contacts are etched through the nitride layer and STI oxide layer, directly to the body tie. This process flow provides a direct body tie contact to mitigate floating body effects but also eliminates hysteresis and transient upset effects common in non-direct body tie contact configurations, without the critical alignment requirements and critical dimension control of the layout.

Direct contact to area efficient body tie process flow

Non-planar SOI devices that include an 'area-efficient' body tie are disclosed. The device includes a bulk substrate, an insulator layer formed on a surface of the bulk substrate, and a silicon body formed on a surface of the insulator layer. The silicon body preferably includes (i) a non-planar channel connecting a source region and a drain region, and (ii) a body tie that is adjacent to the channel and couples the channel to a voltage potential. The device further includes a gate dielectric formed on the channel and a gate material formed on the gate dielectric.

Non-planar silicon-on-insulator device that includes an 'area-efficient' body tie

An Electrically Erasable Programmable Read Only Memory (EEPROM) memory cell and a method of operation are disclosed for creating an EEPROM memory cell in a standard CMOS process. A single polysilicon layer is used in combination with lightly doped MOS capacitors. The lightly doped capacitors employed in the EEPROM memory cell can be asymmetrical in design. Asymmetrical capacitors reduce area. Further capacitance variation caused by inversion can also be reduced by using multiple control capacitors. In addition, the use of multiple tunneling capacitors provides the benefit of customized tunneling paths.

Single-poly EEPROM cell with lightly doped MOS capacitors

The present invention provides silicon based thin-film structures that can be used to form high frequency optical modulators. Devices of the invention are formed as layered structures that have a thin-film dielectric layer, such as silicon dioxide, sandwiched between silicon layers. The silicon layers have high free carrier mobility. In one aspect of the invention a high mobility silicon layer can be provided by crystallizing an amorphous silicon layer. In another aspect of the invention, a high mobility silicon layer can be provided by using selective epitaxial growth and extended lateral overgrowth thereof.

Growing community of inventors

Mound, MN, United States of America

Bradley J Larsen