Freescale Semiconductor,inc.

Motorola Corporation

Bradley J Garni

Thomas Andre

Joseph J Nahas

Chitra K Subramanian

Mark A Durlam

Bradley Neal Engel

Nicholas David Rizzo

Saied N Tehrani

Mark F Deherrera

Perry H Pelley

Ravindraraj Ramaraju

Hector Adrian Sanchez

Kenneth R Burch

David R Bearden

Gregory W Grynkewich

Brian R Butcher

Charles Eric Seaberg

Halbert S Lin

Thomas W Liston

Mark DeHerrera

Glenn E Starnes

Mark W Jetton

Clarance J Tracy

Huy Van V Pham

A bypass system and method that mimics read timing of a memory system which includes a self-timing circuit and a sense amplifier. When prompted, the self-timing circuit initiates the sense amplifier to evaluate its differential input. The bypass system includes a memory controller that is configured to provide a bypass enable, to prompt the self-timing circuit, and to disable normal read control when a bypass read operation is indicated. A bypass latch latches an input data value, converts the input data value into an input complementary pair, and provides the complementary pair to the differential input of the sense amplifier. The sense amplifier, when initiated, evaluates the input complementary pair after its self-timing period and provides an output data value. The bypass latch and self-timing circuit may operate synchronous with a read clock in a read domain of the memory for more accurate memory read timing.

Bypass system and method that mimics clock to data memory read timing

A voltage regulator regulates voltage at a node and has circuitry coupled to the node for providing a current to the node. A regulating transistor coupled between the node and a first power supply voltage terminal has a disabling transistor coupled in parallel and is selectively disabled by directly connecting the first power supply voltage terminal to the node. An inverting stage has an output connected to the regulating transistor. A load transistor has a first current electrode coupled to a second power supply voltage terminal, and a control electrode and second current electrode connected together and coupled to an input of the inverting stage. A sensing transistor has a first current electrode coupled to the second current electrode of the load transistor, a control electrode connected directly to the node and a second current electrode coupled to the first power supply voltage terminal.

Integrated circuit having low power mode voltage regulator

A magnetoresistive random access memory (MRAM) has separate read and write paths. This reduces the peripheral circuitry by not requiring switching between read and write functions on a particular line. By having the paths dedicated to either read signals or write signals, the voltage levels can be optimized for these functions. The select transistors, which are part of only the read function, may be of the low-voltage type because they do not have to receive the relatively higher voltages of the write circuitry. Similarly, the write voltages do not have to be degraded to accommodate the lower-voltage type transistors. The size of the overall memory is kept efficiently small while improving performance. The memory cells are grouped so that adjacent to groups are coupled to a common global bit line which reduces the space required for providing the capacitance-reducing group approach to memory cell selection.

MRAM architecture with electrically isolated read and write circuitry

A sense amplifier () and method for sensing a MRAM cell () is provided. The sense amplifier () includes a precharge circuit (') having an operational amplifier () that uses a voltage divider () in a feedback path to control the amount of charge stored on a capacitor (). During a precharge portion of a read operation, the charge stored on the capacitor () is used to precharge the sense amplifier (). By using charge sharing to precharge the sense amplifier (), the sense amplifier () can be precharged to a steady state common mode voltage more quickly, thus decreasing time required for a read operation.

MRAM sense amplifier having a precharge circuit and method for sensing

An MRAM is provided that minimizes the limits in MRAM density imposed by utilization of an isolation or select device in each memory cell. In addition, methods are provided for reading an MTJ in a ganged memory cell of the MRAM. The method includes determining an electrical value that is at least partially associated with a resistance of a ganged memory cell of the MRAM. The MTJ in the ganged memory cell is toggled and a second electrical value, which is at least partially associated with the resistance of the ganged memory cell, is determined after toggling the MTJ. Once the electrical value prior to the toggling and after the toggling is determined, the difference between the two electrical values is analyzed to determine the value of the MTJ.

MRAM and methods for reading the MRAM

A circuit provides a stress voltage to magnetic tunnel junctions (MTJs), which comprise the storage elements of a magnetoresitive random access memory (MRAM), during an accelerated life test of the MRAM. The stress voltage is selected to provide a predetermined acceleration of aging compared to normal operation. A source follower circuit is used to apply a stress voltage to a subset of the memory cells at given point in time during the life test. The stress voltage is maintained at the desired voltage by a circuit that mocks the loading characteristics of the portion of the memory array being stressed. The result is a closely defined voltage applied to the MTJs so that the magnitude of the acceleration is well defined for all of the memory cells.

Accelerated life test of MRAM cells

An MRAM architecture is provided that reduces the number of isolation transistors. The MRAM architecture includes magnetoresistive memory cells that are electrically coupled to form a ganged memory cell. The magnetoresistive memory cells of the ganged memory cell are formed with Magnetic Tunnel Junctions (MTJs) and formed without isolation devices, such as isolation transistors, and a programming line and a bit line are adjacent to each of the magnetoresistive memory cells. Preferably, the magnetoresistive memory cells of the ganged memory cell only include MTJs, and a programming line and a bit line are adjacent to each of the magnetoresistive memory cells.

MRAM architecture

An integrated circuit () includes electrical circuitry () formed on a substrate (). An interconnect layer () is formed over the electrical circuitry (). In one example, a plurality of magneto-resistive random access memory cells (MRAM) () is implemented above the interconnect layer. Each of the MRAM cells comprises a magneto-resistive tunnel junction (MTJ) storage element. A transistor () is formed-over the interconnect layer (). In one embodiment, the transistor is implemented as a thin film transistor (TFT). In one embodiment the transistor is a select transistor and may be coupled to one or more of the MTJ storage elements. Access circuitry () is formed on the substrate () under the plurality of MRAM cells ().

Integrated circuit with a transitor over an interconnect layer

A sense amplifier ( ) is provided for sensing the state of a toggling type magnetoresistive random access memory (MRAM) cell without using a reference. The sense amplifier ( ) employs a sample-and-hold circuit ( ) combined with a current-to-voltage converter ( ), gain circuit ( ), and cross-coupled latch ( ) to sense the state of a bit. The sense amplifier ( ), first senses and holds a first state of the cell. The cell is toggled to a second state. Then, the sense amplifier ( ) compares the first state to the second state to determine the first state of a toggling type memory cell.

Sense amplifier and method for performing a read operation in a MRAM

The state of a MRAM cell is detected when the magnetic tunnel junction (MTJ) of the MRAM cell has a reduced bias from the maximum voltage that is used for biasing. In one example, the MTJ of the selected cell and the MTJ of a reference cell are both biased to a first voltage. The MTJs then discharge this bias asymptotically (RC time constant based utilizing bit line capacitance and MTJ resistance) to a lower voltage such as ground but at rates that are different for the selected cell versus the reference cell due to MTJ resistance differential. At a predetermined time the voltage differential is detected. In another example, the MTJs are precharged to a low voltage then are driven asymptotically toward a higher voltage. Thus, at the time of sensing for both cases, the voltage across the MTJ is less than the bias voltage that is being used.

Technique for sensing the state of a magneto-resistive random access memory

In a memory, a bias circuit ( ) uses a current reference ( ) for providing a reference current and control circuitry ( ) to bias a sense amplifier ( ) with a varying voltage (V ). The varying voltage maintains current through MRAM bit cells ( ) at a value proportional to the reference current over variations in average bit cell resistance with immunity to variations in process, supply voltage and temperature. In one form, a mock sense amplifier ( ) and mock array of bit cells ( ) are used to establish internal steady state voltages equivalent to a steady state condition of the sense amplifier with equalized outputs and to generate the varying bias voltage. Matching diode-connected transistors in each of the control circuitry and either the mock sense amplifier or the sense amplifier is used to generate the varying bias voltage.

Sense amplifier bias circuit for a memory having at least two distinct resistance states

A magnetoresistive random access memory (MRAM) has separate read and write paths. Switchable current mirrors, each having multiple series-connected stages, receive a common reference current. A timing circuit provides control signals to word and bit decoders and to the switchable current mirrors to selectively complete current paths through a predetermined write word line and a predetermined write bit line. Bit lines are connected together at a common end, and word lines are connected together at a common end. By precharging a common rail having multiple write bit lines connected together, the write noise immunity is improved and current spikes are minimized. Groups of bit lines may be connected via a metal option to adjust a transition time of a programming current.

Memory having write current ramp rate control

A sense amplifier ( ) develops internally a midpoint reference current from two reference bits. The midpoint reference current is used to sense the state of a memory bit having at least two distinct resistance states (H and L) by determining whether the sense memory bit develops a larger or smaller current. The midpoint reference current is developed within a single sense amplifier. Predetermined bias voltages are developed from each of a data bit cell, a reference cell programmed to a high state and a reference cell programmed to a low state. Currents are developed from the bias voltages and summed to create the midpoint reference current. A current differential amplifier senses whether the bit input has a high or low resistive state and outputs a voltage indicative of the sensed memory state.

Sense amplifier incorporating a symmetric midpoint reference

In a memory, a sensing system detects bit states using one data and two reference inputs, to sense a difference in conductance of a selected memory bit cell and a midpoint reference conductance. Reference conductance is generated as the average conductance of a memory cell in the high conductance state and a memory cell in the low conductance state. The data input is coupled to the selected memory bit cell. The two reference inputs are respectively coupled to memory cells in high and low conductance memory states. The sense amplifiers use either current biasing or voltage biasing to apply a sensing voltage within a predetermined voltage range across the bit cells. Capacitance coupled to complementary outputs of the sense amplifiers is balanced by the circuit designs. In one form, the two reference inputs are internally connected. One of several gain stages amplifies the sense amplifier output without injecting parasitic errors.

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Austin, TX, United States of America

Bradley J Garni