Lattice Semiconductor Corporation

Bradley Felton

Ju Shen

Cyrus Y Tsui

Rafael Czernek Camarota

Albert L Chan

Andrew Armitage

Om P Agrawal

Satwant Singh

Chan-Chi Jason Cheng

Jason Cheng

Paul R Bonwick

A programmable logic device includes a plurality of logic blocks organized into a cluster. Each logic block may be configured into a logic mode and a memory mode. The logic blocks are arranged into at least one cluster, each cluster having a data bus configured to provide data words to logic blocks within its cluster.

Programmable logic device with flexible memory allocation and routing

A memory provides a programmable write port data width and an independently programmable read port data width. The independence between the programmable write port data width and the programmable read port data width is achieved without the use of a third clock domain.

FIFO memory with programmable data port widths

A programmable integrated circuit device includes a plurality of output terminals, each output terminal for use in transmitting a respective output signal. Timing control circuitry is connected to the output terminals. The timing control circuitry is operable to delay the output signal on each output terminal and is further operable to control a slew rate of the output signal on each output terminal.

Programmable integrated circuit device with slew control and skew control

A circuit for providing programmable voltage output levels in a logic device includes a pull-up device for driving an output pad with either a first voltage output level or a second voltage output level. A charge pump generates a pumped voltage. A first clamp regulator, coupled to the charge pump and the pull-up device, receives a first reference signal. The first clamp regulator, in response to the first reference signal, generates a first voltage from which the first voltage output level is derived. A second clamp regulator, coupled to the pull-up device, receives a second reference signal. In response to the second reference signal, the second clamp regulator generates a second voltage from which the second voltage output level is derived. A passgate multiplexer is coupled to the first and second clamp regulators. The passgate multiplexer receives at least one output voltage select signal. In response to the at least one output voltage select signal the passgate multiplexer selects either the first voltage output level or the second voltage output level.

Programmable output voltage levels

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Corsham, United Kingdom

Bradley Felton