Emulex Design & Manufacturing Corporation

Emulex Corporation

California Institute of Technology

Bradley Eugene Roach

Peter Mark Fiacco

David James Duckman

Michael Yu Liu

Sam S Su

Qing Xue

Eric David Peel

Stuart B Berman

Karl M Henson

Raul Bersamin Oteyza

Greg Scherer

Vuong Cao Nguyen

Shak Loong Kwok

Embodiments of the present invention are directed to systems and methods for controlling the temperature of an internal device while reducing or minimizing the involvement of the host. Thus, some of the heat monitoring and remediation work may be offloaded to the actual device itself. The device may monitor its own temperature and, in the event of high temperature, perform device specific heat reduction actions without involving the host. Furthermore, the device may, upon detecting temperature within a predefined range, alert the host of a high temperature condition in order to allow the host to perform temperature reduction measures. Also, the device may, upon detecting temperature within a predefined range, alert the host of an impending device shutdown and shut the device down. In addition, the device may periodically save its temperature into non-volatile memory in order to create a temperature log.

Chip overheating protection

Storing frames of data in frame buffers sized to match the frame size when the frame size is not a power-of-two number of bytes is disclosed. The buffer size is chosen to be the largest power-of-two that is less than the frame size. When a frame of data is to be stored, the buffer number of a free buffer is effectively multiplied by the buffer size to obtain a partial frame buffer address Q. The buffer size subtracted from the frame size is referred to as a residual buffer size, and the buffer number is effectively multiplied by the residual buffer size to obtain a residual frame buffer address R. The full frame buffer starting address S=Q+R. For implementations where the difference between the frame size and the buffer size is a power-of-two value, binary shifts and addition can be used instead of a multiplier.

Stacking series of non-power-of-two frame buffers in a memory array

A system with a first random access memory (RAM), a second RAM, a first processor coupled to the first RAM and a second processor coupled to the second RAM. The first RAM is configured to store input/output (I/O) completions from at least two engines. The second RAM is also configured to store I/O completions from at least two engines. When all engines are active, the system writes I/O completions from the engines to the first and second RAMs. The first processor processes I/O completions stored in the first RAM. The second processor processes I/O completions stored in the second RAM.

Supercharge message exchanger

A DMA (Direct Memory Access) Exchange Block (DXB) processor may include a receive processor for writing data from a local memory to a host memory over a bus, e.g., a Peripheral Component Interconnect Extended (PCI/X) bus, and a transmit processor for writing data retrieved from the host memory over the bus to the local memory. Each processor may include a high priority queue and a normal priority queue. A controlling program generates DXBs, each of which include a tag assigned by the controlling program and memory descriptors corresponding to a direct memory access operation. The memory descriptor may include a host memory descriptor (address/length) and one or more local memory descriptors. The controlling program writes a DXB to one of the queues in a cache line spill operation. The transfer processor may include two channel registers, enabling the processor to perform two PCI/X data transfers simultaneously.

Direct memory access (DMA) transfer buffer processor

A memory controller for a multi-byte burst memory device may control access to memory based on parameters set up by a client. These parameters may include a byte address and a byte count that indicates the number of bytes the client is requesting from memory. These values, and an integer representing the number of bytes in a burst-accessed word, may be operated on to produce a word that may be used to identify valid bytes in the burst-accessed word.

Method for determining valid bytes for multiple-byte burst memories

A system with a first random access memory (RAM), a second RAM, a first processor coupled to the first RAM and a second processor coupled to the second RAM. The first RAM is configured to store input/output (I/O) completions from atleast two engines. The second RAM is also configured to store I/O completions from at least two engines. When all engines are active, the system writes I/O completions from the engines to the first and second RAMs. The first processor processes I/O completions stored in the first RAM. The second processor processes I/O completions stored in the second RAM.

A frame receive queue may perform disassembly and validation operations on frames received by a node in a Fiber Channel network. The frame receive queue may store information used for later processing of the frames, e.g., header data and the first eight payload words, in an on-chip memory for fast processor access. The payload data for the frames may be stored in a larger, external memory.

Queuing fibre channel receive frames

A data formatter includes a shift register and a pointer manager. The shift register receives data from a providing RAM and shifts that data in response to reading data from the providing RAM and writing data to a receiving FIFO. A pointer manager maintains a pointer that points to a first valid byte in a sub-block of data into the correct bytes lanes of the FIFO by moving the pointer as data is shifted into and out of the shift register.

Data formatter for shifting data to correct data lanes

A method of validation and host buffer allocation for unmapped fiber channel frames. More particularly, the invention encompasses a method of validating unmapped frames, each including a header and a payload, including receiving a frame as a current frame; determining if the current frame is a first frame in a sequence, and if so, saving the header and payload of the current frame in a buffer, and otherwise determining if the current frame is a next expected frame in the sequence; if the current frame is the next expected frame in the sequence, then saving the payload of the current frame in the buffer after the payload of the prior frame; determining if the current frame is a last frame in the sequence, and if so, sending a message to a host indicating receipt of the complete sequence; if the current frame is not the next expected frame in the sequence, then saving the header and payload of the current frame in the buffer, and sending a message to the host indicating receipt of a partial sequence. The host CPU is interrupted when either a complete sequence is received, or a partial sequence is received, followed by a frame from a different sequence. The host CPU may then process the concatenated payload of the sequence. The invention is particularly useful for processing TCP/IP frames in a Fiber Channel network.

Method of validation and host buffer allocation for unmapped fibre channel frames

A communication processor sends and receives frames of data and commands. Transmit and receive protocol engine is controlled by host driver software which utilizes predetermined bits to indicate which frame is the last frame in a series of frames. This information is then placed in the transmit frame before it is sent.

Communication processor having buffer list modifier control bits

A method and apparatus for processing and transferring frames of data in a computer data link that maps incoming frames to a specific buffer ring in host memory based on routing control and type fields in each frame. More particularly, a Fibre Channel link port contains receiver routing code (RRCode) registers that allow host software to set up routing control (R.sub.-- CTL) match and mask fields, and TYPE match and mask fields. The link port uses these registers to match and mask against corresponding R.sub.-- CTL/TYPE fields in a received frame to determine which of several R.sub.-- CTL/TYPE host memory buffer rings should be used to store the received frame. The link port places a code (RRCode) in a start of frame (SOF) status word associated with a frame. The RRCode indicates a specific R.sub.-- CTL/TYPE host memory buffer ring, or indicates that no match was found or that multiple matches were found. A protocol engine reads the RRCode field in the SOF status word of the received frame, and queues a direct memory access (DMA) operation to an appropriate R.sub.-- CTL/TYPE buffer ring. The host may then process the contents of the indicated buffer ring. Since the buffer rings are 'pre-sorted' as to frame type, the host may more efficiently respond to incoming frames.

Method of mapping fibre channel frames based on control and type header

A full duplex communication processor simultaneously sends and receives frames of data and commands. Separate transmit and receive protocol engines are controlled by separate sequencers. This enables frames of data to be received and transmitted simultaneously without involving a host CPU on a frame-by-frame basis.

Growing community of inventors

Costa Mesa, CA, United States of America

Bradley Eugene Roach