Texas Instruments Corporation

Bradley David Sucher

James Fred Salzman

Weidong Tian

Zafar Imam

Henry Litzmann Edwards

Abbas Ali

Ashesh Parikh

Jeffrey R Debord

Toan Tran

Bernard John Fischer

Binghua Hu

Rick L Wise

Christopher Scott Whitesell

Neil L Gardner

James Hoyt Beatty

Joshua J Hubregsen

Disclosed examples include semiconductor devices and fabrication methods to fabricate semiconductor wafers and integrated circuits, including forming a first epitaxial semiconductor layer of a first conductivity type on a first side of a semiconductor substrate of the first conductivity type, forming a nitride or oxide protection layer on a top side of the first epitaxial semiconductor layer, forming a second epitaxial semiconductor layer of the first conductivity type on the second side of the semiconductor substrate, and removing the protection layer from the first epitaxial semiconductor layer. The wafer can be used to fabricate an integrated circuit by forming a plurality of transistors at least partially on the first epitaxial semiconductor layer.

Process enhancement using double sided epitaxial on substrate

An electronic device includes a semiconductor substrate having a plurality of trenches formed therein. Each trench includes a sidewall having a doped region, a sidewall liner, and a filler material. The substrate has a slip density of less than 5 cm. The low slip density is achieved by a novel annealing protocol performed after implanting the dopant in the sidewall to repair damage and/or stress caused by the implant process.

Anneal after trench sidewall implant to reduce defects

In some examples, a method includes etching a substrate to form a trench, wherein the trench includes sidewalls. The method further includes forming a first isolation region in the trench by growing a first layer of a first thickness on the sidewalls using a dry oxidation technique and depositing a second layer to fill a portion of the trench, the second layer contacting the first layer. The method further includes etching third and fourth layers atop the substrate to expose a first portion of the substrate. The method further includes growing a second isolation region in the substrate through the first portion by using a dry-wet-dry oxidation technique.

Formation of isolation layers using a dry-wet-dry oxidation technique

A method for fabricating an integrated circuit (IC) includes etching trenches into a semiconductor surface of a substrate that has a mask thereon. Trench implanting using an angled implant then forms doped sidewalls of the trenches. Furnace annealing after trench implanting includes a ramp-up portion to a maximum peak temperature range of at least 975&#xb0; C. and ramp-down portion, wherein the ramp-up portion is performed in a non-oxidizing ambient for at least a 100&#xb0; C. temperature ramp portion with an Oflow being less than 0.1 standard liter per minute (SLM). The sidewalls and a bottom of the trench are thermally oxidized to form a liner oxide after furnace annealing to form dielectric lined trenches. The dielectric lined trenches are filled with a fill material, and overburden portions of the fill material are then removed to form filled trenches.

In described examples, an embedded thermoelectric device is formed by forming isolation trenches in a substrate, concurrently between CMOS transistors and between thermoelectric elements of the embedded thermoelectric device. Dielectric material is formed in the isolation trenches to provide field oxide which laterally isolates the CMOS transistors and the thermoelectric elements. Germanium is implanted into the substrate in areas for the thermoelectric elements, and the substrate is subsequently annealed, to provide a germanium density of at least 0.10 atomic percent in the thermoelectric elements between the isolation trenches. The germanium may be implanted before the isolation trenches are formed, after the isolation trenches are formed and before the dielectric material is formed in the isolation trenches, and/or after the dielectric material is formed in the isolation trenches.

CMOS-based thermopile with reduced thermal conductance

An integrated circuit containing CMOS transistors and an embedded thermoelectric device is formed by forming isolation trenches in a substrate, concurrently between the CMOS transistors and between thermoelectric elements of the embedded thermoelectric device. Dielectric material is formed in the isolation trenches to provide field oxide which laterally isolates the CMOS transistors and the thermoelectric elements. Germanium is implanted into the substrate in areas for the thermoelectric elements, and the substrate is subsequently annealed, to provide a germanium density of at least 0.10 atomic percent in the thermoelectric elements between the isolation trenches. The germanium may be implanted before the isolation trenches are formed, after the isolation trenches are formed and before the dielectric material is formed in the isolation trenches, and/or after the dielectric material is formed in the isolation trenches.

A method for fabricating an integrated circuit (IC) includes initial oxidizing of a semiconductor surface of a substrate. The substrate is heated after the initial oxidizing using a plurality of furnace processing steps which each include a peak processing temperature between 800&#xb0; C. and 1300&#xb0; C. The furnace processing steps include at least one accelerated processing step having an accelerated ramp portion in a temperature range between 800&#xb0; C. and 1250&#xb0; C. providing an accelerated ramp-up rate and/or an |accelerated ramp-down rate| of at least (&#x2267;) 5.5&#xb0; C./min.

Accelerated furnace ramp rates for reduced slip

A method of nucleating and growing oxygen precipitates during a pad oxidation process. The nucleating is performed during in the oxidation furnace prior to the pad oxide growth. At least a portion of the growth of the oxygen precipitates occurs during the pad oxide growth. The oxygen precipitates are of sufficient concentration and size in lightly doped p-type wafers for effective gettering of heavy metals is deep submicron transistor, integrated circuit manufacturing flows.

Thermal budget optimization for yield enhancement on bulk silicon wafers

In one aspect provides a method of manufacturing a semiconductor device having improved transistor performance. In one aspect, this improvement is achieved by conducting a pre-deposition spacer deposition process wherein a temperature of a bottom region of a furnace is higher than a temperature of in the top region and is maintained for a predetermined period. The pre-deposition temperature is changed to a deposition temperature, wherein a temperature of the bottom region is lower than a temperature of the top region.

Method of manufacturing a semiconductor device having improved transistor performance

The present invention provides a system for dissipating any aberrant charge that may accumulate during the fabrication of a semiconductor device segment (), obviating overstress or break down damage to a focal device structure () that might result from uncontrolled dissipation of the aberrant charge. A substrate () has first and second intermediate structures () disposed atop the substrate, with the focal structure disposed atop the substrate therebetween. A first conductive structure () is disposed atop the second intermediate structure, the focal structure, and a portion of the first intermediate structure. A third intermediate structure () is disposed contiguously atop the first conductive structure and the first intermediate layer. A void () is formed in a peripheral region () of device segment, through the first and third intermediate layers down to the substrate. A second conductive structure () is disposed atop the third intermediate structure such that it couples the substrate through the void.

Growing community of inventors

Murphy, TX, United States of America

Bradley David Sucher