International Business Machines Corporation

Other

Bradley David McCredie

Leo James Clark

James Stephen Fields, Jr

Frank David Ferraiolo

Ravi Kumar Arimilli

William John Starke

Daniel Mark Dreps

Michael Stephen Floyd

Roger Ned Bailey

Guy L Guthrie

Jerry Don Lewis

Kevin Charles Gower

William Joseph Armstrong

John Michael Borkenhagen

James A O'Connor

Kevin Franklin Reick

David R Engebretsen

Martin Joseph Crippen

Dhruv Manmohandas Desai

Philip Rogers Hillier, Iii

James Edward Hughes

Steven M Tri

Jennifer Lane Vargus

Michael Gerard Nealon

Hugh Rodney Stigdon

Paul William Coteus

Frank Eliot Levine

Naresh Nayar

William Gavin Holland

Lee Evan Eisen

Wiren Dale Becker

Edward Hugh Welbon

Andreas Bieswanger

Norman Karl James

Larry Scott Leitner

George A Katopis

Carl J Anderson

Craig R Selinger

Charles Kyriakos Vakirtzis

Toru Kobayashi

Daniel John Kolor

Hideo Sawamoto

William G Hollan

Gerald W Mahoney

Techniques are disclosed for reducing impact of a repair action in a switch fabric. In one embodiment, a server system is provided that includes a first interposer card that operatively connects one or more server cards to a midplane. The first interposer card may include a switch module that switches network traffic for the one or more server cards. The first interposer card may be hot-swappable from the midplane, and the one or more server cards may be hot-swappable from the first interposer card.

Reducing impact of a repair action in a switch fabric

A method, system, and device for enabling intervention across same-level cache memories. In a preferred embodiment, responsive to a cache miss in a first cache memory a direct intervention request is sent from the first cache memory to a second cache memory requesting a direct intervention that satisfies the cache miss. In an alternate embodiment, direct intervention is utilized to access a same-level victim cache.

Victim cache using direct intervention

A method, apparatus and computer instructions are provided to autonomically monitor and adjust system characteristics based on a customer optimization goal specified in a policy or profile. An autonomic management component is implemented in firmware comprising a set of control algorithms. Response to reading system characteristics from a plurality of sensors, the autononmic management component selects at least one control algorithm from the set and the control algorithm adjusts the parameters of the system characteristic to optimize performance according to the optimization goal specified by the customer.

Method and apparatus for autonomic policy-based thermal management in a data processing system

An apparatus and method for accurately tuning the speed of an integrated circuit, i.e. a computer chip, using a built-in sense circuit and controller are provided. The sense circuit is provided in association with a monitored path. The sense circuit includes a variable delay element coupled to a controller. A data signal from the monitored path is provided to the sense circuit which adds an amount of delay as determined by the controller to the data signal. The delayed data signal and the original data signal are compared to determine if their values match. If they match, then the amount of delay added by the variable delay element is increased. If they do not match, then a previous amount of delay, prior to the mismatch, is output as the slack of the monitored path. The slack may then be used to tune the speed of the integrated circuit.

Apparatus and method for accurately tuning the speed of an integrated circuit

A multi-chip apparatus is disclosed. In one form, the apparatus includes a carrier having a number of integrated circuit chips electrically coupled in a communications ring. The communications ring has carrier portions on the carrier and chip portions traversing the respective chips, permitting the communications ring carrier portions to be substantially straight, whereas at least one of the chip portions has a turn, enabling closure of the ring. In another aspect, the chips include respective regeneration circuitry interposed in the respective chip portions of the communications ring, for regenerating communications signals traversing the respective chips on the respective chip portions of the ring.

Multi-chip module having chips coupled in a ring

A method and apparatus are disclosed for communicating between a master and slave device. A sequence of data sets and a clock signal (&ldquo;Bus clock&rdquo;) are sent from the master to the slave, wherein the successive sets are asserted by the master at a certain frequency, each set being asserted for a certain time interval. The data and Bus clock are received by the slave, including capturing the data by the slave, responsive to the received Bus clock. The slave generates, from the received Bus clock, a clock (&ldquo;Local clock&rdquo;) for clocking operations on the slave. The sequence of the received data sets is held in a sequence of latches in the slave, each set being held for a time interval that is longer than the certain time interval for which the set was asserted by the master. The data sets are read in their respective sequence from the latches, responsive to the Local clock, so that the holding of respective data sets for the relatively longer time intervals in multiple latches and the reading of the data in sequence increases allowable skew of the Local clock relative to the received Bus clock.

Elastic interface for master-slave communication

A Fully Interconnected System Architecture (FISA) for an improved data processing system. The data processing system topology has a processor chip and external components to the processor chip, such as memory and input/output (I/O) and other processor chips. The processor chip is interconnected to the external components via a point-to-point bus topology controlled by an intra-chip integrated, distributed switch (IDS) controller. The IDS controller provides the chip with the functionality to provide a single bus to each external component and provides an overall total bandwidth greater than traditional topologies while reducing latencies between the processor and the external components. The design of the processor chip with the intra-chip IDS controller provides a pseudo &ldquo;distributed switch&rdquo; which may separately access distributed external components, such as memory and I/Os, etc.

Data processing system with fully interconnected system architecture (FISA)

A method and system for dynamic synchronization of a data processing system processor chips. One of a plurality of chips is designated as a primary chip and all other chips as secondary chips. The clock phase of the chips are synchronized utilizing the primary chip's clock phase as a reference clock phase for the secondary chips.

Method and system for data processing system self-synchronization

A signal is transmitted from a sending chip to a first receiving chip in a communications ring via a first i/o set of the sending chip. A signal from the sending chip to a second receiving chip in the communications ring is transmitted via a second i/o set of the sending chip. The first i/o set corresponds to a first direction for the sending chip transmitting around the ring, and the second i/o set corresponds to a second direction for the sending chip transmitting around the ring. The transmitting via the first i/o set is for a circumstance where a number of chips interposed in the ring between the sending and receiving chips in the first direction is not greater than the number of chips interposed in the second direction. The transmitting via the second i/o set is for a circumstance where the number is greater. For a chip interposed between the sending and receiving chips, the transmitting includes traversing from one of the first and second i/o sets of the at least one interposed chip, to the other one of the first and second i/o sets of the at least one interposed chip. The signal traversing the at least one interposed chip is regenerated by the interposed chip.

Communication method for integrated circuit chips on a multi-chip module

A method and system for increasing speeds of transferring data in a data transfer system which includes a data source and data sink. Both the data source and data sink include clocks which are synchronized to a common clock frequency. A buffer is provided at the data sink and this buffer is utilized to received data from the data source. A control circuit is provided at the data sink and this control circuit receives a bus clock signal from the data source. An N segment dynamic shift register is provided within the data sink which includes at least two segments. A selectable shift control is provided for passing the data through an M segment subset of the N segment shift register, where M is less than N. Additionally, the length of the M segment subset is determined by the phase of a clock within the data sink at the time which the bus clock signal from the data source is received at the data sink. By selectively passing the data through an M segment subset of the N segment shift register, the data is accessible at the data sink at a controllable predetermined time.

Method and system for data transfer

The foregoing objects are achieved as is now described. A method and system for testing an integrated circuit are provided. A test substrate is provided which is manufactured by the same particular production technology for which the complex integrated circuit is designed. A pattern generator for generating test data and a result checker for comparing output data are embedded on the test substrate. Isolated portions of circuitry of the integrated circuit are selectively embedded onto the test substrate. The isolated portions of circuitry are subjected to testing by applying test data from the pattern generator to the isolated portions of circuitry. Errors in the isolated portions of circuitry are detected with the result checker by comparing data output from the isolated portions of circuitry with predetermined expected data, such that the integrated circuit is tested by susets, independently of testing the integrated circuit in its entirety.

Method and system for testing an integrated circuit

A data processing system having a modified processor chip and external components to the processor chip. The processor chip is interconnected to the external components via point-to-point bus connections controlled by an integrated distributed switch (IDS) controller. The IDS controller is placed, during chip design, in the upper layer metals of the processor chip. When the data processing system is a multi-chip multiprocessor data processing system, the IDS controller operates to provide a pseudo switching effect whereby the processor is directly connected to each external component. The IDS controller permits the processor to have greater communication bandwidth and reduced latencies with the external components. It also allows for a connection to distributed external components such as memory and I/O, etc. with overall reduced system components.

Multiprocessor system with a high performance integrated distributed switch (IDS) controller

A method and system for testing an integrated circuit. A test substrate is provided which is manufactured by the same particular production technology for which the integrated circuit is designed. A pattern generator for generating test data and a result checker for comparing output data are embedded on the test substrate. Isolated portions of circuitry of the integrated circuit are selectively embedded onto the test substrate. Test data from the pattern generator is applied to the isolated portions of circuitry under a first operating condition. The data output from the isolated portions of circuitry is selectively recorded into the result checker. The isolated portions of circuitry are then subjected to testing by applying test data from the pattern generator to the isolated portions of circuitry under a second operating condition. Errors in the isolated portions of circuitry are detected with the result checker by comparing data output from the isolated portions of circuitry with the selectively recorded data output, such that the integrated circuit is tested by subsets, independently of testing the integrated circuit in its entirety.

Method and system for performing pseudo-random testing of an integrated circuit

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Austin, TX, United States of America

Bradley David McCredie