Intel Corporation

Bradford B Congdon

Kenneth C Creta

Robert T George

Michael J McTague

Tony S Rand

Rama U Reddy

Robert G Blankenship

Duane January

Mike Bell

Deepak Ramachandran

A network management card is provided to capture a screen image of a host system for transmission over a computer network for remote viewing and remote system management. The network management card is provided with a processor which processes a program to implement a video capture sequence of operations; and a bus controller having operations controlled by the processor, which tracks events on a bus of the host system, including operations of a video subsystem of the host system, and which executes a video capture sequence of operations to capture a screen image provided by the video subsystem of the host system for transmission to a remote system over a computer network or other communications link for remote viewing and remote system management.

Network management card for use in a system for screen image capturing

A computer chipset having an identifier module and a router. The identifier module is configured to add sequence identifiers to each transaction in independent ordered sequences of transactions. The sequence identifiers identify which ordered sequence the transactions belong to. The identifier module combines the ordered sequences of transactions into a combined ordered sequence of transactions. The combined ordered sequence of transactions are sent over an ordered interface. A router then separates the combined ordered sequence of transactions into ordered queues based on the sequence identifiers associated with the transactions. The transactions in the ordered queues are executed in an order that reduces the time required to complete the transactions.

Reordering unrelated transactions from an ordered interface

An input/output hub includes an inbound ordering queue (IOQ) to receive inbound transactions. All read and write transactions have a transaction completion. Peer-to-peer transactions are not permitted to reach a destination until after all prior writes in the IOQ have been completed. A write in a peer-to-peer transaction does not permit subsequent accesses to proceed until the write is guaranteed to be in an ordered domain of the destination. An IOQ read bypass buffer is provided to receive read transactions pushed from the IOQ to permit posted writes and read/write completions to progress through the IOQ. An outbound ordering queue (OOQ) stores outbound transactions and completions of the inbound transactions. The OOQ also issues write completions for posted writes. An OOQ read bypass buffer is provided to receive read transactions pushed from the OOQ to permit posted writes and read/write completions to progress through the OOQ. An unordered domain within the input/output hub receives the inbound transactions transmitted from the IOQ and receives the outbound transactions transmitted from an unordered protocol.

Mechanism for preserving producer-consumer ordering across an unordered interface

A caching input/output hub includes a host interface to connect with a host. At least one input/output interface is provided to connect with an input/output device. A write cache manages memory writes initiated by the input/output device. At least one read cache, separate from the write cache, provides a low-latency copy of data that is most likely to be used. The at least one read cache is in communication with the write cache. A cache directory is also provided to track cache lines in the write cache and the at least one read cache. The cache directory is in communication with the write cache and the at least one read cache.

Distributed read and write caching implementation for optimized input/output applications

A user-friendly, PCI bus-compliant plug-in management card is provided to evaluate a PCI bus in a host computer system for correct operation. The PCI management card is provided with a PCI bus controller ASIC for tracking error and fault conditions which may occur on a PCI bus and reporting such error and fault conditions locally or remotely over a computer network. The PCI bus controller ASIC may be implemented with a reset snoop which snoops the PCI bus for a bus reset; a clock snoop which snoops the PCI bus for a bus clock changing frequency or dying; a cycle timer which begins counting when a bus cycle starts, resets the counting when the bus cycle ends, and triggers an alarm indicating a hung cycle when the bus cycle has not ended after a predetermined time period; a cycle snoop which snoops the bus for any illegal handshake and any hung cycle triggered from the cycle timer; and an error capture which captures all error and failure conditions snooped from the reset snoop, the clock snoop, the cycle timer, and reports such error and failure conditions to a local processor for transmission to a host system, or to a remote system over a computer network for remote system management.

Bus management card for use in a system for bus monitoring

A method and apparatus for masking processor requests to improve bus efficiency includes a bus bridge having a detection logic for determining when a first processor on a first bus has been backed off the first bus a predetermined number of times. When the detection logic determines the first processor has been backed off the first bus the predetermined number of times, a timer is set to a first value, with the first value being sufficient to allow an agent on a second bus to access the first bus. A masking logic, coupled to the detection logic and the timer, is for masking requests from the first processor until the timer expires.

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Olympia, WA, United States of America

Bradford B Congdon