Other

Advanced Micro Devices Corporation

Brad T Moore

Daniel Kadosh

Jon D Cheek

Mark I Gardner

Fred N Hause

Robert Louis Dawson

Michael P Duane

Gregory D Smith

A system for tracking and managing baking pans and trays, comprising a set of baking pans or trays that includes a plurality of individual baking pans or trays, each of which includes a unique identification tag positioned thereon, wherein each unique identification tag includes information about the individual baking pan or tray on which the identification tag is positioned; and a data acquisition system that includes at least one sensor mounted in proximity to a production line conveyor for detecting baking pans or trays positioned on the conveyor; at least one tag-reading device that is activated when the at least one sensor detects a pan or tray on the conveyor, wherein the at least one tag reading device reads information from each identification tag and transmits the information to a controller; and a controller that includes hardware and software that controls the at least one sensor and the at least one tag reading device, and that receives, processes, and outputs the information read from the identification tags on the baking pans or trays.

Automated tracking system for baking pans and trays

Various processes are provided for producing a p-channel and/or n-channel transistor. The present processes are thereby applicable to NMOS, PMOS or CMOS integrated circuits, any of which derive a benefit from having an asymmetrical LDD structure. The asymmetrical structure can be produced on a p-channel or n-channel transistor in various ways. According, the present process employs various techniques to form an asymmetrical transistor. The various techniques employ processing steps which vary depending upon the LDD result desired. First, the LDD implant can be performed only in the drain-side of the channel, or in the drain-side as well as the source-side. Second, the gate conductor sidewall surface adjacent the drain can be made thicker than the sidewall surface adjacent the source. Thickening of the drain-side sidewall spacer can be achieved either by depositing oxide upon a nitride-bearing film, or by growing additional oxide upon an exposed silicon surface having the source-side sidewall protected from growth. Third, the drain-side can be enhanced relative to the source-side by using an LTA implant. There may be numerous other modifications and alternative processing steps, all of which are described herein. Regardless of the sequence chosen, a barrier implant may be employed to prevent deleterious ingress of p-type implant species into the channel region. The present fabrication sequence reduces source-side resistance to enhance drive current--a desirable outcome for high speed circuits.

Asymmetrical transistor structure

Various processes are provided for producing a p-channel and/or n-channel transistor. The present processes are thereby applicable to NMOS, PMOS or CMOS integrated circuits, any of which derive a benefit from having an asymmetrical LDD structure. The asymmetrical structure can be produced on a p-channel or n-channel transistor in various ways. According, the present process employs various techniques to form an asymmetrical transistor. The various techniques employ processing steps which vary depending upon the LDD result desired. First the LDD implant can be performed only in the drain-side of the channel, or in the drain-side as well as the source-side. Second, the gate conductor sidewall surface adjacent the drain can be made thicker than the sidewall surface adjacent the source. Thickening of the drain-side sidewall spacer can be achieved either by depositing oxide upon a nitride-bearing film, or by growing additional oxide upon an exposed silicon surface having the source-side sidewall protected from growth. Third, the drain-side can be enhanced relative to the source-side by using an LTA implant. There may be numerous other modifications and alternative processing steps, all of which are described herein. Regardless of the sequence chosen, a barrier implant may be employed to prevent deleterious ingress of p-type implant species into the channel region. The present fabrication sequence reduces source-side resistance to enhance drive current--a desirable outcome for high speed circuits.

Asymmetrical n-channel transistor having LDD implant only in the drain

Asymmetrical p-channel transistor having a boron migration barrier and

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Austin, TX, United States of America

Brad T Moore