Lattice Semiconductor Corporation

Advanced Micro Devices Corporation

Vantis Corporation

Brad Sharpe-Geisler

Ting Yew

Bai Yen Nguyen

Giap H Tran

Senani Gunaratna

Om P Agrawal

Kiet Truong

Satwant Singh

Fabiano Fontana

Henry Law

Sam Tsai

Keith Truong

Ravi Lall

Timothy Scott Swensen

Jye-Yuh Lee

Sunil D Mehta

Ronald L Cline

Loren McLaury

Chan-Chi Jason Cheng

Steven J Fong

Ban Pak Wong

Kuang Chi

Qin Wei

Chwei-Po Chew

Siak Chon Kee

Melvin D Chan

Cindy Lee

Systems and methods for providing external bus protection for programmable logic devices (PLDs) are disclosed. An example system includes a programmable I/O bus configured to interface with a user device over an external bus interface coupled to a PLD; a bus protection circuit arrangement integrated with the programmable I/O interface and configured to provide I/O bus supply voltage protection for the programmable I/O interface; and a bus protection control signal generator. The bus protection control signal generator generates a default bus protection control signal for the bus protection circuit arrangement of the PLD prior to completion of a power ramp performed by the user device; an intermediate bus protection control signal for the PLD prior to completion of loading a PLD configuration into a PLD fabric of the PLD; and an operational bus protection control signal for the PLD.

Input/output bus protection systems and methods for programmable logic devices

Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a programmable logic device (PLD) includes a plurality of programmable logic blocks (PLBs) and at least first and second logic cells within at least one of the PLBs, where each logic cell includes a lookup table (LUT) and associated mode logic configured to receive a LUT output signal from the LUT. The associated mode logic is configured to use a single physical signal output to provide a logic cell output signal corresponding to a selected logic function operational mode, ripple arithmetic operational mode, or extended logic function operational mode for each logic cell.

Multiple mode device implementation for programmable logic devices

Various techniques are provided to efficiently implement deterministic read back and error detection for programmable logic devices (PLDs). In one example, a PLD includes an array of memory cells arranged in rows and columns, where at least one row includes an enable bit. The PLD further includes an address logic circuit configured to selectively assert the columns of the array by respective address lines. The PLD further includes a register configured to store a value of the enable bit in response to an assertion of an address line corresponding to the enable bit. The PLD further includes a read back circuit configured to selectively provide, for each memory cell, a data bit value stored by the memory cell or a predetermined data bit value based at least on the stored value of the register. Additional systems and related methods are provided.

Deterministic read back and error detection for programmable logic devices

Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a programmable logic device (PLD) includes a plurality of programmable logic blocks (PLBs) and a plurality of logic cells within at least one of the PLBs, where each logic cell includes a four input lookup table (4-LUT) configured to provide a 4-LUT output signal to associated carry logic. Each logic cell is configurable according to at least two selectable operational modes including a logic function output mode and a ripple arithmetic output mode, and at least three of the 4-LUT inputs are interchangeable when a selected operational mode comprises the ripple arithmetic output mode.

Flexible ripple mode device implementation for programmable logic devices

Various techniques are provided to efficiently implement selective power gating of routing resource configuration memory bits for programmable logic devices (PLDs). In one example, a PLD includes a routing circuit configured to selectively route input nodes to an output node. The PLD further includes configuration memory cells configured to store configuration bit values to control the routing circuit. The PLD further includes a power circuit configured to power the configuration memory cells while storing the configuration bit values. The PLD further includes an enable bit memory cell configured to store an enable bit value to interrupt at least one connection of the power circuit to the configuration memory cells. The configuration memory cells are configured to provide, in response to an interruption of the connection, default configuration bit values to the routing circuit to prevent routing the input nodes to the output node. Additional systems and related methods are provided.

Selective power gating of routing resource configuration memory bits for programmable logic devices

A programmable logic is provided that uses only NMOS pass transistors to pass a true output signal to an internal true node and to pass a complement output signal to an internal complement node. The internal true and complement nodes are cross-coupled through PMOS transistors so that the discharge of one of the internal true and complement nodes switches on a corresponding one of the cross-coupled PMOS transistors to charge a remaining one of the internal true and complement nodes.

High speed complementary NMOS LUT logic

In one embodiment, an integrated circuit includes multiple I/O banks, each bank having multiple I/O-ESD tiles, each tile having one or more I/O circuits and electrostatic discharge (ESD) protection circuitry for the one or more I/O circuits in the tile. The ESD circuitry for one tile includes at least one RC-triggered clamp, whose resistance is provided by a resistor shared by one or more other RC-triggered clamps in one or more other tiles of the same bank and whose capacitance is provided by a combination of distributed capacitors, one for each of those two or more RC-triggered clamps. Each tile may have multiple instances of such RC-triggered clamps providing ESD protection for different (e.g., power supply and/or bus) nodes. The shared resistors are variable to allow different instances of the same ESD circuitry design to be implemented with the same time constant for different banks having different numbers of tiles.

ESD protection using shared RC trigger

In one embodiment, an integrated circuit has hot-socket circuitry to protect I/O drivers during hot-socket events. The hot-socket circuitry has (i) N-well-to-pad switcher circuitry that ties driver PMOS N-wells to pads when the pad voltages are greater than the power-supply voltage and (ii) N-well-to-power-supply switcher circuitry that ties the driver PMOS N-wells to the power supply when the pad voltages are less than the power-supply voltage. The hot-socket circuitry also has a special PMOS device connected between the pad and a gate of at least one other PMOS device in the N-well-to-power-supply switcher circuitry to turn off the N-well-to-power-supply switcher circuitry quickly whenever the pad voltage is greater than the power-supply voltage. Applying a reduced power-supply voltage level to the gate of the special PMOS device enables the hot-socket circuitry to be implemented without having to use low Vt devices and without having to implement substantially large drive strengths.

Hot-socket circuitry

In one integrated circuit embodiment, a programmable pull-down output buffer is calibrated by sequentially configuring the buffer at different drive-strength levels and adjusting a source current applied to the buffer until the voltage at an input node of the buffer reaches a reference voltage level. A programmable pull-up output buffer is then calibrated by sequentially configuring a pull-down output buffer based on the pull-down buffer calibration results and adjusting the drive-strength level of the pull-up buffer until the voltage at a common node between the two buffers reaches a reference voltage level. Average calibration results are generated by averaging multiple calibration results for each setting. Output buffers are thereby calibrated to compensate for PVT variations without using any external resistors and without requiring any I/O pins of the integrated circuit.

PVT compensation scheme for output buffers

A control circuit is provided that enables a register to provide a synchronous initialization capability as well as an asynchronous capability despite the register having no asynchronous input.

Shared logic for multiple registers with asynchronous initialization

In one embodiment, a memory includes a plurality of bit lines and a write driver for driving a driven bit line selected from the plurality of bit lines during a write operation. The write driver is coupled to an internal node. A first stage clamping circuit is operable to clamp the internal node to a clamping voltage if the write operation is not enabled and is further operable to unclamp the internal node during the write operation. The memory further includes a multiplexer for selectively coupling the driven bit line to the internal node. A second stage clamping circuit is operable to clamp the plurality of bit lines to a clamping voltage if the write operation is not enabled and is further operable to unclamp the driven bit line during the write operation.

Dual-port SRAM with bit line clamping

A ball-grid-array (BGA) package is disclosed that includes traces within a BGA substrate. At least one of the traces is configured to match a low-impedance load presented by a BGA substrate pad and associated circuitry on a flip-chip die to an impedance of a circuit board trace. Each configured trace includes a relatively narrow section coupling to a tapered section that widens from the relatively narrow section to join a relatively wider trace section.

Growing community of inventors

San Jose, CA, United States of America

Brad Sharpe-Geisler