Altera Corporation

Brad Ishihara

Krishna Rangasayee

Robert N Bielby

Kunio Nishiwaki

A method of programming and verifying a macroscale based architecture in a field programmable logic device includes the step of selecting a flip-flop. The flip-flop contains a programmable address that accepts a sequence of instructions. A Switch Controller then selectably enables either one of two banks of switches. If the first bank of switches is selected, the programming operation is selected. If the second bank of switches is enabled, the verification operation is selected. The verification operation includes the step of automatically incrementing a base address through a set of incremented addresses. For each incremented address produced by the incrementing step, a margin low operation is performed with a Level Tester Array and a margin high operation is performed with a Level Tester Array. Thus, unlike the prior art, margin operations with the present invention are performed without using a macrocell scan register. Advantageously, relatively large groups of data are loaded into the flip-flops in the ADSR to improve processing.

Apparatus and method for verifying macrocell base field programmable logic devices

A programmable logic device has buffers that may be selectively programmed for Schmitt-triggered and threshold-triggered operation. The programmable Schmitt-triggered buffers are connected to circuit nodes that are sensitive to noisy environments. The programmable threshold-triggered buffers are connected to circuit nodes that have critical timing requirements.

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Sunnyvale, CA, United States of America

Brad Ishihara