Intel Corporation

Brad Heaney

Sundari S Mitra

Andy Hou

Timing signals governing the precharge and evaluation phases of a PLA are generated by internal circuitry so that the PLA can be maintained in a fully static mode without destroying data integrity and without dissipating a significant amount of power. 'Dummy' lines connected at every programmable intersection are added to the PLA to provide a measure of the maximum propagation delay. The evaluation phase of the PLA is terminated closely following the maximum propagation delay and precharging is begun soon thereafter. The timing ensures that evaluation completes, valid data is latched and the PLA is returned to a precharge condition even if the phase clock signals are suspended and regardless of the states of the phase clock signals when suspended.

Programmable logic array with internally generated precharge and

An input to the control unit of a microprocessor places the microprocessor in a WAIT condition whenever the input clock frequency is determined to be less than a predetermined minimum value. A timing circuit which includes a relatively high capacitance device generates a 'kill' signal whenever the time interval between successive clock pulses is greater than a value corresponding to a cut-off frequency. The kill signal is applied to the control unit of the microprocessor and cannot be reset except with a system reset.

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Mountain View, CA, United States of America

Brad Heaney