Motorola Corporation

Brad D Gunter

Danny A Bersch

David J Anderson

Howard C Anderson

Doug Garrity

Douglas Alan Garrity

A programmable capacitor array (10, 10') and a method for programming the programmable capacitor array (10, 10'). The programmable capacitor array (10, 10') includes an array of capacitors (C.sub.0 -C.sub.n), wherein each capacitor of the array of capacitors (C.sub.0 -C.sub.n) has first and second terminals. The first terminal of each capacitor may be coupled to a first circuit node (11) or to a first reference terminal (13). Likewise, the second terminal of each capacitor may be coupled to a second circuit node (12) or to a second reference terminal (14). One or more capacitors of the array of capacitors (C.sub.0 -C.sub.n) may be selectively coupled across the first (11) and second (12) circuit nodes or coupled across the first (13) and second (14) reference terminals, thereby permitting each capacitor to be electrically isolated from the array of capacitors (C.sub.0 -C.sub.n).

Programmable capacitor array and method of programming

A circuit and method for reducing voltage error when charging and discharging a storage capacitor (44) through a transmission gate (43). The storage capacitor (44) stores or holds a voltage coupled through the transmission gate (43) when the transmission gate (43) is disabled. The circuit comprises a clock generation circuit (47) providing complementary clock signals for enabling and disabling the transmission gate (43) and a charge negating transmission gate (46). The clock generation circuit (47) provides the complementary clock signals simultaneously to the transmission gates (43, 46). Alternate paths for dissipating channel charge of the transistors which comprise the transmission gate (43) are not formed by providing the complementary clock signals simultaneously. The channel charge is then canceled by the charge negating transmission gate (46) reducing voltage error on the storage capacitor (44).

Circuits and method for reducing voltage error when charging and

A circuit and method for reducing voltage error when charging and discharging a variable capacitor (44) through a switch (43). The switch (43) comprises a plurality of transmission gates (53-55) coupled in parallel. A control circuit (42) provides control signals for enabling transmission gates of the plurality of transmission gates (53-55). The control circuit (42) changes the resistance of the switch (43) by selecting an appropriate transmission gate wherein each transmission gate has a different resistance. The resistance of the switch (43) is varied as a capacitance of the variable capacitor (44) is changed to maintain a predetermined RC time constant over the entire range of capacitor values of the variable capacitor (44).

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Phoenix, AZ, United States of America

Brad D Gunter