International Business Machines Corporation

Motorola Corporation

Brad B Beavers

Chih-Jui Peng

Lew G Chua-Eoan

Pei-Chun Peter Liu

Robert Alan Cargnoni

Jose Melanio Nunez

Michael Scott Allen

David W Todd

Chua-Eoan Lew

Jen-Tian Yen

The present invention provides a system and method for efficient execution of load reserve (LARX) and store conditional (STCX) instructions in a superscalar processor. A system for efficiently providing a LARX instruction in a superscalar processor is disclosed. The system comprises a data cache (Dcache) for receiving the LARX instruction. The data cache further includes a decoder means for setting and resetting of a validation of the load reserve instruction, an internal cache for receiving address information and for providing data. The system also includes a register means for receiving the LARX instruction and a controller means for providing a physical address based upon the address information. The system provides for the validation being accomplished in one cycle for the LARX instruction when there is a hit on the internal data cache.

High performance implementation of the load reserve instruction in a

A fully associative address translator which includes a number of entries, each of said number of entries translating a received effective address into a real address, each received effective address including a segment identifier and a page identifier. Each of the entries within the fully associative address translator includes a first translation from an effective address segment identifier into a virtual address segment identifier and a second translation from a virtual address page identifier to a real address page identifier. A first valid bit cell is provided for storing a validity bit which indicates the validity of the first translation from the effective address segment identifier to the virtual address segment identifier and a second valid bit cell is also provided for storing a validity bit indicating the validity of the second translation from the virtual address page identifier to the real address page identifier wherein a process context switch will invalidate only a portion of each of the entries, thereby reducing the miss penalty associated with a context switch.

Fully associative address translation buffer having separate segment and

A CAM/SRAM structure (44) performs address translations that are compatible with a segmentation/paging addressing scheme yet require only a single look-up step. Each entry in the effective-to-real-address-translator (ERAT) has two CAM fields (ESID, EPI) that independently compare an input segment identifier and an input page identifier to a stored segment identifier and a stored page identifier, respectively. The ERAT outputs a stored real address field (DATA) associated with a stored segment-stored page pair if both comparisons are equivalent. The ERAT can invalidate stored translations on the basis of segment or page granularity by requiring either a segment or a page CAM field match, respectively, during an invalidate operation.

Single array address translator with segment and page invalidate ability

An address translator (126) translates addresses, acting like a register file or a table, as necessary. The address translator contains a number of entries for matching an input address to a stored tag. An entry outputs a stored translated address if its stored tag matches the input address. A decoder (138) selects a particular entry in which to store an input translated address when the address translator operates as a register file. In these cases, a register number is also stored in the particular entry's as the entry's tag. Later, when it is necessary to read the particular entry, the register number is compared to each entry's tag to find a match. The disclosed address translator is compatible with both hardware and software refill algorithms ('tablewalks') without impacting its critical read speed path.

Address translator and method of operation

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Austin, TX, United States of America

Brad B Beavers