Samsung Electronics Co., Ltd.

Boyoung Seo

Yongkyu Lee

Gwanhyeob Koh

Taejoong Song

Yongtae Kim

Suk-Soo Pyo

Hyuntaek Jung

Kangho Lee

Choong Jae Lee

Seongui Seo

Seungchul Jung

Sangjoon Kim

Yoonjong Song

KeeMoon Chun

Junghoon Bak

Junghyuk Lee

Yongsang Jeong

Youngmok Kim

Myoungsu Son

ChangMin Jeon

Byungsup Shim

Kyunglyong Kang

Jungu Kang

Teakwang Yu

Hyucksoo Yang

A magnetic memory device includes a plurality of first bit lines and a plurality of second bit lines, a plurality of first source lines respectively corresponding to the plurality of first bit lines and a plurality of second source lines respectively corresponding to the plurality of second bit lines, a plurality of first memory cells connected between the plurality of first bit lines and the plurality of first source lines, respectively, in a first region, the plurality of first memory cells respectively including a first memory device and a first selection transistor, and a plurality of second memory cells connected between the plurality of second bit lines and the plurality of second source lines, respectively, in a second region, the plurality of second memory cells respectively including a second memory device and a second selection transistor.

Magnetic memory device

Provided is a processing device having improved reliability and power consumption efficiency of analog calculations as well as high cost efficiency due to reduction in a size of a bit-cell, and an electronic system including the processing device. The processing device includes: at least one bit-cell line on which a plurality of bit-cells are connected to each other in series, wherein each of the bit-cells includes: a first magnetic tunnel junction (MTJ) element; a second MTJ element connected to the first MTJ element in parallel; a first switching element connected to the first MTJ element in series; and a second switching element connected to the second MTJ element in series, and wherein on the bit-cell line, two adjacent bit-cells are connected to each other in series in a mirroring structure.

Processing device based on magnetic tunnel junction (MTJ) element and electronic system including the processing device

A display apparatus includes a display panel; and a display driver integrated circuit (DDI) chip coupled to the display panel, the DDI chip being configured to generate a display driving signal for driving the display panel based on image data. The DDI chip may include: a first embedded memory device embedded in the DDI chip and configured to store compensation data for compensating for electrical and optical characteristics of a plurality of pixels included in the display panel; a timing controller configured to control signals for driving the display panel, and to generate a data control signal based on the image data and the compensation data; and a data driver configured to provide a data voltage to the display panel according to the data control signal. The first embedded memory device may not include static random access memory (SRAM).

Display driver integrated circuit (DDI) chip and display apparatus

A nonvolatile memory device includes a first variable resistance element connected to a first bit line, and a first transmission ;ate connected between the first variable resistance element and a first source line. The first transmission gate includes a first insulating layer formed on a well connected to aground voltage, a first n-channel metal oxide semiconductor (NMOS) transistor formed on the first insulating layer and connected to a first word line, a second insulating layer formed on the well, the second insulating layer being in the same layer as the first insulating layer, and a first p-channel metal oxide semiconductor (PMOS) transistor formed on the second insulating layer and connected to a first write word line.

Nonvolatile memory device and operating method thereof

A magnetic memory device includes a substrate, a landing pad on the substrate, first and second magnetic tunnel junction patterns disposed on the interlayer insulating layer and spaced apart from the landing pad when viewed from a plan view, and an interconnection structure electrically connecting a top surface of the second magnetic tunnel junction pattern to the landing pad. A distance between the landing pad and the first magnetic tunnel junction pattern is greater than a distance between the first and second magnetic tunnel junction patterns, and a distance between the landing pad and the second magnetic tunnel junction pattern is greater than the distance between the first and second magnetic tunnel junction patterns, when viewed from a plan view.

Magnetic memory devices

A semiconductor device includes a memory cell array, which further includes an array of first magnetic memory cells and an array of second magnetic memory cells. Each of the first magnetic memory cells includes a first magnetic tunnel junction structure having a reversible resistance state, and each of the second magnetic memory cells includes a second magnetic tunnel junction structure having a one-time programmable (OTP) resistance state.

Semiconductor devices including reversible and one-time programmable magnetic tunnel junctions

A variable resistance memory device includes different variable resistance patterns on different memory regions of a substrate. The different variable resistance patterns may be at different heights from the substrate and may have different intrinsic properties. The different variable resistance patterns may at least partially comprise separate memory cells that are each configured to function as a non-volatile memory cell or a random access memory cell, respectively.

Variable resistance memory devices

An operating method of a nonvolatile memory device includes storing different data in first and second reference cells connected to a word line, checking whether the different data are abnormally stored in the first and second reference cells, and when it is determined that the different data are abnormally stored in the first and second reference cells, swapping the first and second reference cells.

Disclosed is a method of fabricating a magnetic memory device. The method of a fabricating a magnetic memory device includes forming an interlayer dielectric layer on a substrate, forming a sacrificial pattern in the interlayer dielectric layer, forming a magnetic tunnel junction pattern on the sacrificial pattern, after forming the magnetic tunnel junction pattern, selectively removing the sacrificial pattern to form a bottom contact region in the interlayer dielectric layer, and forming a bottom contact in the bottom contact region.

Methods of fabricating magnetic memory devices

A logic embedded nonvolatile memory device is provided which includes a first erase gate line for erasing a plurality of first memory cells; a second erase gate line electrically separated from the first erase gate line and for erasing a plurality of second memory cells; a global erase gate line supplied with an erase voltage; and an erase gate selection switch formed between the first memory cells and the second memory cells, wherein the erase gate selection switch connects the global erase gate line to the first erase gate line or the second erase gate line according to an erase control signal.

Logic embedded nonvolatile memory device

The inventive concepts provide a semiconductor memory device including variable resistance memory elements. The semiconductor memory device may include a first bit line disposed at a first height from a semiconductor substrate, a second bit line disposed at a second height, which is different from the first height, from the semiconductor substrate, a first variable resistance memory element connected to the first bit line, and a second variable resistance memory element connected to the second bit line. The first and second variable resistance memory elements may be disposed at substantially the same height from the semiconductor substrate.

Semiconductor memory device

Nonvolatile memory devices can include a floating gate on a substrate, with a first tunnel insulating film therebetween. A memory gate can be on the floating gate, with a blocking insulating film therebetween. A word line can be located at a first side of both the memory gate and the floating gate, with a second tunnel insulating film therebetween. The first side of the floating gate can protrude beyond the first side of the memory gate toward the word line.

Growing community of inventors

Suwon-si, South Korea

Boyoung Seo