Samsung Display Co., Ltd.

BoYong Chung

Jonghee Kim

Sang-uk Lim

Bogyeong Kim

Doo-young Lee

Tak-Young Lee

Hyuk Hwan Kim

Byungseok Choi

Takyoung Lee

Tak-young Lee

Sanguk Lim

Dooyoung Lee

Chang-soo Lee

Doo-Young Lee

A display device includes a display panel and a gate driver. The gate driver includes an N-th stage (where N is a natural number) configured to output an N-th scan gate signal and output an N-th sensing gate signal. The N-th stage includes a compensator, a sixth transistor including a control electrode connected to a first node, and a ninth transistor including a control electrode connected to the first node. In a variable frequency mode, the compensator outputs a second signal to the first node in response to a first signal, and the sixth transistor does not output the N-th scan gate signal when the ninth transistor outputs the N-th sensing gate signal based on the sensing clock signal, the voltage of the first node, and the voltage of the second node.

Display device

A gate driving circuit includes a stage which outputs a scan signal based on a scan clock signal, a voltage of a first node, and a voltage of a second node, and outputs a sensing signal based on a sensing clock signal, a voltage of the first node, and a voltage of the second node. The stage includes a second sensing portion including transistors electrically connected in series and a first pull-up control portion including transistors electrically connected in series, the transistors including control electrodes electrically connected to each other. A first intermediate node between the transistors of the second sensing portion is separated from a second intermediate node between the transistors of the first pull-up control portion.

Gate driving circuit and display device including the same

A display device includes a display panel including a plurality of pixels respectively connected to a plurality of data lines and a plurality of scan lines, a data driver which outputs data signals to the plurality of data lines including a first data line and a second data line branched from a data output terminal connected to the data driver, and a scan driver which outputs scan signals to the plurality of scan lines. A first scan output terminal and a second scan output terminal respectively connected to the plurality of scan lines are connected to the scan driver. One of the first scan output terminal and the second scan output terminal is connected to a resistance.

Provided is a gate driving circuit comprising an N-th stage and an N+1-th stage. The N-th stage outputs an N-th scan gate signal based on an N-th scan clock signal, a voltage of a QN node, and a voltage of a QBN node and to output an N-th carry signal based on an N-th carry clock signal, the voltage of the QN node, and the voltage of the QBN node. The N+1-th stage outputs an N+1-th scan gate signal based on an N+1-th scan clock signal, a voltage of a QN+1 node, and the voltage of the QBN node and an N+1-th carry signal based on an N+1-th carry clock signal, the voltage of the QN+1 node, and the voltage of the QBN node. The N-th stage and the N+1-th stage share an inverting circuit. The inverting circuit controls the QBN node based on a third signal. N is a positive integer.

Gate driving circuit and display apparatus including the same

A display device includes a substrate, a first conductive layer disposed on the substrate, a second conductive layer disposed on the first conductive layer and a third conductive layer disposed on the second conductive layer. The first conductive layer includes a data line extending in a first direction. The second conductive layer includes a first scan line extending in a second direction intersecting the first direction, and a second scan line spaced apart from the first scan line and extending in the second direction. The third conductive layer includes a first driving voltage line extending in the second direction, a first common voltage line spaced apart from the first driving voltage line and extending in the second direction, and a pixel electrode disposed between the first driving voltage line and the first common voltage line in a plan view.

A scan driver includes stages, and first to third clock signals are applied to the stages, respectively. A falling time of the first clock signal is shorter than falling times of the second and third clock signals.

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Yongin-si, South Korea

BoYong Chung