Cirrus Logic Inc.

Lexar

Boyd Gayle Pett

Petro Estakhri

Mahmud M Assar

Vlad Bril

A computer card including a voltage detection circuit having Flash EEPROM devices and a controller device, the voltage detection circuit further including a variable voltage detector for determining the system voltage level provided by a power supply within the computer product and appropriately enabling a voltage regulator circuit for dividing the system voltage level to a level suited for operation by the Flash EEPROM devices and applying this operational voltage level to the Flash EEPROM devices. Upon determining the system voltage level provided by the power supply to be appropriately suited for operation of the Flash EEPROM devices, disabling the voltage regulator circuit and providing the system voltage level to the Flash EEPROM devices.

Automatic voltage detection in multiple voltage applications

Modifications to a prior art system known as video graphics adapter (VGA) for displaying color images on a monitor attached to a personal computer. The modifications provide the following four enhancements to a standard VGA system: (i) user definable border color; (ii) automatic powering down of the digital analog converter (DAC) component of the VGA RAMDAC and monitor sense comparator for LCD monitors when the RAMDAC is not in use; (iii) stopping of the RAMDAC clock for LCD monitors when the RAMDAC is not in use; and (iv) true color support.

VGA color system for personal computers

A low power clocking circuit includes a crystal oscillator for generating a digital signal having a first frequency. The first frequency is relatively slow which allows the crystal oscillator to consume reduced power. The phase detector signal is coupled to control a charge pump circuit that generates a voltage on an output node for controlling a voltage controlled oscillator. The VCO generates a clock signal having a second frequency that is higher than the first frequency. The charge pump circuit includes an active mode and a power down mode and is operatively coupled between a first supply voltage and a second supply voltage. As typically provided, the charge pump includes a capacitor network coupled to the output node for maintaining the output voltage. The charge pump includes a voltage control circuit having an up input for increasing the output voltage and a down input for decreasing the output voltage. In addition, a ring enable input is provided for open circuiting all electrical paths from the first supply voltage to the second supply voltage and a precharge circuit is provided for maintaining the output voltage at a predetermined precharge level during the power down mode. Finally, a jump start input controls a jump start circuit for rapidly driving the output voltage to a predetermined level while the charge pump circuit transitions from a power down mode to an active mode. The jump start input includes a single pulse of the digital signal.

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San Jose, CA, United States of America

Boyd Gayle Pett