Honeywell Information Systems Inc.

Boyd E Darden

Henry F Hartley

Jian-Kuo Shen

John J Bradley

Ming T Miu

Robert C Miller

Theodore R Staplin, Jr

In a data processing system which includes one or more common buses to which a plurality of input/output controllers are connected for the transfer of data, blocks of data may be transferred between main memory and an input/output controller (IOC) synchronously with operation of the central processor unit (CPU). Logic is provided for enabling one unit of data to be transferred during a Data Multiplex Control (DMC) data transfer operation in which the requesting IOC requests a DMC data transfer of the CPU and later provides the CPU with a channel number assigned to the requesting IOC. In order to allow a data entry operator inputting data via a peripheral device connected to an IOC the ability to correct errors, a backspace character is provided so that the operator can enter it to indicate to the system to ignore the preceding character. Logic is provided within the system to allow a DMC IOC to detect the output of a backspace character from the peripheral device connected to the IOC and to inform the CPU of the entry of the backspace character by a special (backspace) input/output interrupt. Further logic is provided within the CPU to adjust pointers to the main memory input buffer to effectively ignore the byte of data corresponding to the character preceding the backspace character. Still further logic is provided within the DMC IOC to prohibit the sending of special (backspace) input/output interrupts to the CPU if there are no bytes of data remaining in the input buffer.

Data processing system having data entry backspace character apparatus

A data processing system includes a central processing unit, a main store and device controllers which couple to a bus system. Each controller has a number of device adapter units. One controller includes a real time adapter unit which instead of being connected to control a peripheral device is connected to provide a timer facility for use by the central processing unit (CPU) in executing tasks. The real time adapter unit includes a microprocessing section, a timer section, and a module time of day section. The time of day includes circuits which are connected to provide accurate and reliable time of day values. The timer module section includes circuits which are connected to provide variable time intervals. The circuits of both sections are connected to the circuits of the microprocessing section. In response to a number of different commands received from the central processing unit, the microprocessing unit (MPU) of the microprocessing section loads the various registers included within the timer module section to establish a desired interval at which it is to monitor the time of day operation of the time of day section. When the microprocessing unit establishes that the particular time of day operation specified by the central processing unit has been completed, it generates signals for notifying the central processing unit.

Adapter unit for use in a data processing system for processing a

A data processing system includes a central processing unit, a main store and device controllers which couple to a bus system. Each controller has a number of device adapter units. One controller includes a real time adapter unit which instead of being connected to control a peripheral device is connected to provide a timer facility for use by the central processing unit in executing tasks. The real time adapter unit includes microprocessing circuits and clock circuits. These circuits are connected to provide accurate and reliable time of day values in response to commands from the central processing unit.

Growing community of inventors

St. Petersburg, FL, United States of America

Boyd E Darden