Samsung Electronics Co., Ltd.

Seoul National University

Boun Yoon

Ilyoung Yoon

Jeongnam Han

Sangjine Park

Byoungho Kwon

Yanghee Lee

Jonghyuk Park

Sukhun Choi

Hoyoung Kim

Byung-Kwon Cho

Kuntack Lee

Young-Hoo Kim

Jae-Jik Baek

Jaeseok Kim

Kee-Sang Kwon

Chungki Min

Ki-Hyung Ko

Kichul Park

Sangkyun Kim

Ki Hoon Jang

Myunggeun Song

Youngok Kim

Heesook Cheon

Kee Sang Kwon

Jaeung Koo

Wonsang Choi

Hyosan Lee

Sang Won Bae

Jinwoo Bae

Ki-Woong Kim

Miso Shin

Jiwon Yun

Bo Kyeong Kang

Inkwon Kim

Chae Lyoung Kim

Kwansung Kim

Injoon Yeo

Myeongan Kwon

Daehyuk Kang

Jeehwan Heo

Youngbeom Pyon

Yeryung Jeon

Seunghoon Choi

Seungjae Lee

Jongwon Lee

Donghyun Kim

Wandon Kim

Jung-Min Oh

Daeik Kim

Jin-Young Lee

Sanghyun Park

Myung Geun Song

Seung Hoon Choi

Taeyong Kwon

Hyo-Jung Kim

Hayoung Jeon

Tae-Hong Kim

Ju-hyun Kim

Ingi Kim

Eunji Park

Seokhan Park

Young Suk Jung

Do Yoon Kim

Doo-Sung Yun

Kenji Takai

Donghoon Kwon

Taek Dong Chung

Sung-Min Cho

Chang-Sun Hwang

Jeonghyuk Yim

Yungjun Kim

Changki Hong

Bo Yun Kim

Hyesung Park

Imsoo Park

Sol Han

Sukhoon Jeong

Kevin Ahn

Kangchun Lee

Hansol Seok

Kieun Seo

Youngsuk Lee

Seungho Han

Boyun Kim

Ki Ho Bae

KyungTae Lee

Sangline Park

Wongsang Choi

Jeongman Han

Se Jung Park

Sang Yeob Han

Yooyong Lee

Kiho Bae

Ilsu Park

Jaeyong Han

Junseop Lee

Youngho Koh

Myungjae Jang

Choongseob Shin

Hyojin Oh

A semiconductor device may include a substrate, a patterned structure, a filling pattern, and a conductive spacer. The substrate may include a semiconductor chip region and an overlay region. The patterned structure may include bit line structures spaced by a first distance on the semiconductor region, define a first trench and a second trench on first and second regions of the overlay region, and include key structures on the second region and spaced apart by the second trench. The filling pattern may fill lower portions of the first and second trenches on the first and second regions. The first region may be an edge portion of the overlay region. The second region may be a central portion of the overlay region. The conductive spacer may contact an upper surface of the filling pattern and may be on an upper sidewall of each of the first and second trenches.

Semiconductor device

A semiconductor device manufacturing method is capable of manufacturing a semiconductor device with improved reliability, by simplifying a chemical mechanical polishing (CMP) process and minimizing a thickness distribution of a dummy gate during the CMP process. The semiconductor device manufacturing method includes forming, on a substrate, dummy gate structures extending in a first direction and spaced apart from each other in a second direction perpendicular to the first direction, each dummy gate structure including a dummy gate and a mask pattern on an upper surface of the dummy gate; forming an interlayer insulating layer covering the dummy gate structures; and performing the single slurry CMP process of removing some of the interlayer insulating layer and the dummy gate structures through the single slurry CMP process and exposing the upper surface of the dummy gate.

Method of manufacturing semiconductor device using single slurry chemical mechanical polishing (CMP) process

A semiconductor device may include a substrate including an active pattern extending in a first direction, a gate electrode extending in a second direction and crossing the active pattern, a gate capping pattern covering a top surface of the gate electrode, and a separation structure at a side of the gate electrode and extending in the second direction to penetrate the active pattern in a third direction. The first and second directions are parallel to a bottom surface of the substrate and are perpendicular to the third direction. The separation structure may include a filling pattern, which extends in the third direction to penetrate the active pattern, and a vertical insulating pattern, which is interposed between the filling pattern and the gate electrode. A top surface of the separation structure may be located at a height lower than a top surface of the gate capping pattern.

A semiconductor device includes a first substrate; circuit elements on the first substrate; lower interconnection lines electrically connected to the circuit elements; a second substrate on the lower interconnection lines; gate electrodes spaced apart from each other and stacked on the second substrate in a first direction that is perpendicular to an upper surface of the second substrate; channel structures penetrating through the gate electrodes, extending in the first direction, and respectively including a channel layer; through-vias extending in the first direction and electrically connecting at least one of the gate electrodes or the channel structures to the circuit elements; an insulating region surrounding side surfaces of through-vias; and a via pad between the through-vias and at least one of the lower interconnection lines in the first direction and spaced apart from the second substrate in a second direction, parallel to an upper surface of the second substrate.

Semiconductor devices and data storage systems including the same

A semiconductor device may include a substrate including a cell region and a peripheral region, lower electrodes on the cell region of the substrate, a dielectric layer on surfaces of the lower electrodes, a silicon germanium layer on the dielectric layer, a metal plate pattern and a polishing stop layer pattern stacked on the silicon germanium layer, and upper contact plugs physically contacting an upper surface of the silicon germanium layer. The upper contact plugs may have an upper surface farther away from the substrate than an upper surface of the polishing stop layer pattern. The upper contact plugs may be spaced apart from the metal plate pattern and the polishing stop layer pattern.

A semiconductor device includes a substrate including first and second region, a bit line structure on the first region, key structures on the second region, each key structure having an upper surface substantially coplanar with an upper surface of the bit line structure, a first trench disposed between two adjacent key structures spaced apart from each other in a first direction, a filling pattern in a lower portion of the first trench, the filling pattern having a flat upper surface and including a first conductive material, and a first conductive structure on the flat upper surface of the filling pattern, an upper sidewall of the first trench, and the upper surface of each of the plurality of key structures, the first conductive structure including a second conductive material.

Semiconductor devices and methods of manufacturing the same

A method of manufacturing a semiconductor device includes: forming a lower structure that includes a substrate and conductive lines on the substrate, within a chip region and an edge region of the lower structure; forming data storage structures on the chip region of the lower structure; forming dummy structures on the edge region of the lower structure; forming an interlayer insulating layer covering the data storage structures and the dummy structures on the lower structure, the interlayer insulating layer including high step portions and low step portions, an upper end of the low step portions being lower than an upper end of the high step portions; and planarizing the interlayer insulating layer.

Method of manufacturing semiconductor device

A semiconductor device including a substrate; a gate structure on the substrate; a gate spacer on a sidewall of the gate structure; and a polishing stop pattern on the gate structure and the gate spacer, the polishing stop pattern including a first portion covering an upper surface of the gate structure and an upper surface of the gate spacer; and a second portion extending from the first portion in a vertical direction substantially perpendicular to an upper surface of the substrate, wherein an upper surface of a central portion of the first portion of the polishing stop pattern is higher than an upper surface of an edge portion of the first portion thereof, and the upper surface of the central portion of the first portion of the polishing stop pattern is substantially coplanar with an upper surface of the second portion thereof.

Semiconductor devices

A method of manufacturing a metal structure including forming a metal layer including a metal and a nano-abrasive and supplying slurry on the metal layer to perform chemical mechanical polishing, a metal structure including a metal and a nano-abrasive having an average particle diameter of less than about 5 nanometers, and a metal wire, a semiconductor device, and an electronic device including the same.

Metal structure and method of manufacturing the same and metal wire and semiconductor device and electronic device

A semiconductor device including a substrate having a cell region and a peripheral region; a cell gate structure disposed on the cell region; a first impurity region and a second impurity region, arranged on first and second sides of the cell gate structure in the cell region; a bit line structure disposed on the cell gate structure and connected to the first impurity region; a peripheral gate structure disposed on the peripheral region; a peripheral capping layer disposed on the peripheral region, covering the peripheral gate structure, and having an upper surface at substantially the same level as an upper end of the bit line structure; and a cell contact structure disposed on the second impurity region, and having a conductive barrier and a contact material layer on the conductive barrier, wherein the conductive barrier covers the upper end of the bit line structure.

Semiconductor device and a fabrication method thereof

A slurry composition is disclosed which includes: a corrosion inhibitor including a material selected from carbon allotropes and derivatives thereof; and an oxidant. A method of manufacturing an integrated circuit device is disclosed which includes: forming a first metal film and a second metal film on a substrate, the first metal film and the second metal film respectively including different metals; and polishing, by using the slurry composition, a polishing target surface at which the first metal film and the second metal film are exposed.

Slurry composition and method of manufacturing integrated circuit device by using the same

A semiconductor device and a method of fabricating a semiconductor device, the semiconductor device including a semiconductor substrate including a first region and a second region; an interlayer insulating layer on the semiconductor substrate, the interlayer insulating layer including a first opening on the first region and having a first width; and a second opening on the second region and having a second width, the second width being greater than the first width; at least one first metal pattern filling the first opening; a second metal pattern in the second opening; and a filling pattern on the second metal pattern in the second opening, wherein the at least one first metal pattern and the second metal pattern each include a same first metal material, and the filling pattern is formed of a non-metal material.

Semiconductor device including interconnections having different structures and method of fabricating the same

Provided are a three-dimensional semiconductor memory device and a method of fabricating the same. The device may include a substrate including a peripheral circuit region and a cell array region, peripheral gate stacks provided on the peripheral circuit region of the substrate, and an electrode structure provided on the cell array region of the substrate. The electrode structure may include a lower electrode, a lower insulating layer covering the lower electrode, and upper electrodes and upper insulating layers, which are vertically and alternately stacked on the lower insulating layer. The lower insulating layer may be extended from the cell array region to the peripheral circuit region to cover the peripheral gate stacks, and a top surface of the lower insulating layer may be higher on the peripheral circuit region than on the cell array region.

Three-dimensional semiconductor memory device

Growing community of inventors

Seoul, South Korea

Boun Yoon