Tdk Corporation

Northrop Grumman Systems Corporation

Microsoft Technology Licensing, LLC

Other

Bouchaib Cherif

Max Earl Nielsen

Philippe Pouliquen

Dev Vrat Gupta

Abbie Mathew

Isidoros Doxas

Mohammed Wasef

Robert John March, Iii

The proposed dynamic current-mode finite impulse response (FIR) filter includes a coefficient signal generator to generate a coefficient signal, an input signal generator to generate an input signal, a dynamic current multiplier configured to receive the input signal and the coefficient signal and to generate intermediate product terms that are multiplications of the coefficient values and reflected and shifted input values, and an accumulator configured to receive the intermediate product terms and to sequentially integrate the intermediate product terms over the coefficient values to produce output responses for the input values. The dynamic current multiplier includes a first dynamically configured transistor (DCT) having a first input node to receive the first input signal during a first phase of operation and a second input node to receive the second input signal during a second phase of operation, and a second DCT having an input node to receive a third input signal during a first phase of operation, and output the intermediate product terms during a second phase of operation.

Dynamic current-mode finite impulse response filter

According to some other aspects of the present disclosure, an electrical circuit comprises a first capacitive element, a first transistor, a second capacitive element, and a second transistor. The circuit receives a first input current, a second input current, a third input current, and an input voltage. The circuit is configured to generate a first voltage by providing the input voltage and the first input current to the first transistor. The first voltage difference is the difference between the first voltage and the input voltage, and is logarithmically related to the first input current. The circuit may also be configured to store the first voltage as the first charged state of the first capacitive element. The circuit is further configured to generate a second voltage by providing the second input current and the first charged state of the first capacitive element to the first transistor. The second voltage difference is the difference between the first voltage and the second voltage, and is logarithmically related to the second input current. The circuit is additionally configured to generate a third voltage by providing the second voltage and the third input current to the second transistor. The third voltage difference is the difference between the third voltage and the second voltage, and is logarithmically related to the third input current. The circuit may also be configured to store the third voltage as the second charged state of the second capacitive element. The circuit is further configured to generate an output current by providing the input voltage and the second charged state of the second capacitive element to the second transistor. The output current is exponentially related to the fourth voltage difference, which is the difference between the third voltage and the input voltage. The output current is equivalent to a ratio of a product of the first and third input currents to the second input current.

Dynamic translinear current multiplier for analog computing

Phase detectors are provided. In one example, The phase detector may include a first transistor leg and a second transistor leg. Each of the first transistor leg and the second transistor leg may include a pair of transistors coupled together at a plurality of common nodes. The phase detector may include an input at the first transistor leg. The input may be configured to receive a first input signal and a second input signal. The phase detect may include an output coupled to the second transistor leg. The output may be configured to provide an output signal. The output signal may include a component indicative of a phase difference between the first input signal and the second input signal.

Low power phase detector

Trap circuits for use with superconducting integrated circuits having differential capacitively-coupled resonant clock networks are described. An example superconducting integrated circuit (IC) includes a first superconducting circuit comprising: (1) a first Josephson junction (JJ) coupled via a first capacitor to a first clock line, where the first capacitor is configured to receive a first clock signal having a first phase via the first clock line and couple a first bias current to the first JJ, and (2) a second JJ coupled via a second capacitor to a second clock line, where the second capacitor is configured to receive a second clock signal having a second phase via the second clock line and couple a second bias current to the second JJ. The superconducting IC further includes a first trap circuit for the first superconducting circuit and a second trap circuit for a second superconducting circuit having additional JJs.

Trap circuits for use with differential capacitively-coupled resonant clock networks

Trap circuits for use with superconducting integrated circuits having capacitively-coupled resonant clock networks are described. An example superconducting integrated circuit (IC) includes a clock structure coupled: (1) to a first Josephson junction (JJ) via a first capacitor, where the first capacitor is configured to receive a clock signal via the clock structure and couple a first bias current to the first JJ, and (2) to a second JJ via a second capacitor, where the second capacitor is configured to receive a clock signal via the clock structure and couple a second bias current to the second JJ. The superconducting IC further includes a trap circuit coupled between the first capacitor and the first JJ, where the trap circuit is configured to attenuate any signals generated by a triggering of the first JJ to reduce crosstalk between the first JJ and the second JJ.

Trap circuits for use with capacitively-coupled resonant clock networks

One example includes a clock distribution resonator system. The system includes a clock source configured to generate a clock signal having a predefined wavelength. The system also includes a plurality of transmission line branches each coupled to the clock source to propagate the clock signal. The system also includes a plurality of clock distribution networks coupled to the respective plurality of transmission line branches and being configured to provide the clock signal to each of a plurality of circuits. The system further includes at least one damping resonator. Each of the at least one damping resonator can be coupled to a respective at least one of the transmission line branches and configured to propagate the clock signal. The at least one damping resonator can have at least one resonator characteristic that is different relative to a respective resonator characteristic(s) associated with the transmission line branches and/or the clock distribution networks.

Clock distribution resonator system

Techniques for implementing tunable lumped element filters with transmission line sections. Transmission lines sections are used to implement one or more inductive or capacitance component elements of the filter. The filter is tunable by changing the dielectric constants of the transmission lines. In particular implementations there is an individual transmission line section for each lumped element component of a filter. Different filter circuits may be combined to provide a universal tunable filter assembly.

Tunable filter using variable impedance transmission lines

A tunable filter design. The filter is implemented using transmission line sections as inductive and capacitive components. At least one capacitive component is a tunable capacitor. In some implementations, the tunable capacitor may be an interdigitated array of finger elements arranged so that the spacing between fingers may be adjusted. The design has a number of advantages including high capacitance for a given circuit area, small area for a given desired capacitance, mechanical stability, high self resonance frequency, and high quality factor.

Transmission line filter with tunable capacitor

A variable capacitor structure using calibration plates, dual variable distance calibration plates, and/or interleaving extentions to the calibration plates.

Piezo controlled variable capacitor

A tunable capacitor implemented as interdigitated arrays of finger elements arranged so that the spacing between finger arrays may be adjusted. The design has a number of advantages including high capacitance for a given circuit area, small area for a given desired capacitance, mechanical stability, high self resonance frequency, and high quality factor.

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Yorktown Heights, NY, United States of America

Bouchaib Cherif