Zilog, Inc.

Boubekeur Benhamida

Gyle Dee Yearsley

Stephen H Chan

Grant B Richards

Jim Nobugaki

Delay circuitry is used in a circuit to delay the transmission of groups of data until another circuit expects these groups of data. In one embodiment, emulating circuitry is used to emulate the timing of transmitter and receiver UART FIFOs. This emulating circuitry uses delays equal to the amount of time the UART FIFOs take to serially shift out data in the transmitter UART FIFO, and to serially shift in data in the receiver UART FIFO. This allows the modem chip to use a parallel-to-parallel FIFO buffer for the transmitter FIFO buffer and the receiver FIFO buffer.

Delayed FIFO status for serial shift emulation

A self-configurable clock circuit which automatically detects at power up whether an off-chip crystal oscillator is connected to an integrated circuit including the self-configurable clock circuit, and following such detection generates a system clock signal and a power on reset signal to be used by other circuitry included in the integrated circuit. If the off-chip crystal oscillator is connected to the integrated circuit, then the self-configurable clock circuit provides the system clock signal from a first signal generated from the off-chip crystal oscillator. On the other hand, if the off-chip crystal oscillator is not connected to the integrated circuit, then the self-configurable clock circuit provides the system clock signal from a second signal generated from an on-chip RC oscillator circuit.

Circuit for automatically detecting off-chip, crystal or on-chip, RC

A flag setting, reading and clearing circuit is described which includes self arbitrating logic to provide priority for the flag setting portion of the circuit over the flag clearing portion. The flag is set by a set flag signal generated by a portion of a computer system to which the flag setting, reading and clearing circuit is a part. The set flag signal sets the flag by latching the voltage level of a voltage supply to a node in the circuit. A read status signal then latches the voltage at the node to another location which other portions of the computer system can access. At the same time, the read status signal clears the voltage level at the node unless the self arbitrating logic prevents it from doing so. The self arbitrating logic prevents the clearing portion of the circuit from clearing the flag when the set flag signal and the read status signal are both activated or HIGH at the same time. It does this by effectively canceling a control signal to the clearing portion of the circuit which is activated by the read status signal.

Self arbitrating auto resettable flag circuit

An address detection circuit is described having a node A which is precharged to the voltage of a power supply and then discharged down to ground by a strobe signal if an address match occurs. An address match is detected when a nonconventional CMOS inverter which has its input connected to node A has its output go HIGH. The nonconventional CMOS inverter utilizes a device ratio between its P-mos transistor and its N-mos transistor of approximately 10 to 1 for a 1 micron CMOS process. Prior to the strobe signal discharging the node A to ground, the output of the nonconventional inverter is held to ground by a transistor which is switched OFF when the strobe signal discharging the node A to ground is initiated.

Decoder circuit with bypass circuitry and reduced input capacitance for

A domino-logic decoder which decodes an input in an amount of time substantially independent on the bit size of the input. An address is input to a stack of at least two individually gated transistors in the decoder. A first node at one end of the stack is connected to a charge restoring transistor and a strobing transistor, both coupled to a strobe signal. A second node coupled to the strobing transistor provides the decoder output and operably indicates that a particular portion of the decoder has been selected. During operation, the first node is charged and the second node is isolated from the first node by the strobing transistor. After the inputs have fully charged the input transistors and a path to ground is formed, the first node will be discharged. The second node is discharged across the strobing transistor during the strobe phase, indicating that a particular decoder portion has been chosen. Body effect is also eliminated.

Domino-logic decoder

A circuit, which may be included as part of an integrated circuit chip including a microprocessor or other device needing initialization when being powered up, generates a reset signal at a time determined by the voltage rise characteristics of the power supply to the device when either initially turned on to the device or recovering from a voltage dip. A power supply sensing node of the circuit is initially discharged to ground potential in order to eliminate any effect of a charge on the node on the timing of the reset signal, such as might be generated by an ambient electromagnetic field.

Integrated power-on reset circuit

A circuit has a mask option for choosing between a crystal or an RC oscillator. The RC oscillator is completely fabricated on an integrated-circuit chip and includes a charging path, a discharging path, and a capacitor coupled at a node. The alternating charging and discharging of the node produces the oscillating output voltage signal at certain frequency. The oscillation frequency may be trimmed by coupling a single optional external resistor to either the charging or discharging paths, thereby reducing the output oscillation frequency.

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Boise, ID, United States of America

Boubekeur Benhamida